On Tuesday, 14 March 2017 at 19:32:57 UTC, H. S. Teoh wrote:
On Tue, Mar 14, 2017 at 06:50:07PM +0000, Nick B via
Digitalmars-d-announce wrote:
On Tuesday, 14 March 2017 at 13:38:09 UTC, jmh530 wrote:
> On Tuesday, 14 March 2017 at 08:21:03 UTC, Andrea Fontana
> wrote:
> >
> > It seems public:
> > http://insidehpc.com/2017/02/john-gustafson-presents-beyond-floating-point-next-generation-computer-arithmetic/
>
> Also in pdf here
> http://web.stanford.edu/class/ee380/Abstracts/170201-slides.pdf
Thank you both for posting these links :).
[...]
Indeed.
But while the .pdf mentions Posits and Valids, the following
slides only discuss Posits. Where's the discussion on Valids?
In spite of that, though, Posits appear to be a much better
candidate at replacing IEEE 794 floats than the previous unum
incarnations. I felt the previous incarnations, while clever
and workable in theory, posed too many practical challenges to
implement on silicon. The current description of Posits seem
to be much more feasible to put on silicon.
Still, though, I wonder what Gustafson has up his sleeves wrt.
Valids.
In the Stanford presentation pdf, (note that these change from
presentation to presentation) on page 12, is the only mention of
Valids. I thought these were a rename of Sets of Real
Numbers(SORNS) from his Type 2 Unums, but after reviewing the
slides again, I'm not sure. I believe that this needs to be
vertified with Dr Gustafson, as you correctly point out there are
no examples of Valids.
But when I review his slides from his New Zealand talk, there is
an additional slide, where he states that (1) "Posit pairs beat
intervals at their own games, too: Valid mode." and (2) "Posit
mode: Round unum after every operation. Valid mode: rigorous
answer bounds; NaN answers are sets. "
If anyone wants a copy of these New Zealand slides, please advise
me of your email address.
