On Wednesday, 2 April 2014 at 19:29:29 UTC, Ola Fosheim Grøstad
wrote:
On Wednesday, 2 April 2014 at 18:21:26 UTC, deadalnix wrote:
You don't even come close to L3 in 3 cycles. Propagating signal
takes time. You end up with 2 constraint in tension: the bigger
your cache, the longer the round trip.
I was thinking about it the wrong way, I guess it does not
matter if a read is getting the wrong value if there are
concurrent writes to the same location when there is no
synchronization. It's feels weird, but speculative out-of-order
execution etc is not-very-intuitive in the first place...
Yes this mechanism can cause memory operation to be seen out of
order by other cores.
