On 4/4/2016 2:05 PM, 9il wrote:
- Count of FP/Integer registers
??
How many general purpose registers, SIMD Floating Point registers, SIMD Integer
registers have a CPU?
These are deducible from X86, X86_64, and SIMD version identifiers.
Needs to know is it AVX or AVX2 in compile time
Since the compiler never generates AVX or AVX2 instructions, there is no purpose
to setting such as a predefined version identifier. You might as well use a:
-version=AVX
switch. Note that it is a very bad idea for a compiler to detect the CPU it is
running on and default generate code specific to that CPU.
(this may be completely different source code for this cases).
It's entirely practical to compile code with different source code, link them
*both* into the executable, and switch between them based on runtime detection
of the CPU.
We have LDC and GDC. And looks like a little bit standardization based on DMD
would be good, even if this would be useless for DMD.
There is no such thing as a standard compiler floating point switch, and I'm
doubtful defining one would be practical or make much of any sense.
With compile time information about CPU it is possible to always have fast
generic BLAS for any target as soon as LLVM is released for this target.
The SIMD instruction set is highly resistant to transforming generic code into
optimal vector instructions. Yes, I know about auto-vectorization, and in
general it is a doomed and unworkable technology.
http://www.amazon.com/dp/0974364924
It's gotta be done by hand to get it to fly.
