Re: LDC, ARM: unnecessary default initialization

[Jack Applegame via Digitalmars-d]

On Friday, 18 August 2017 at 17:28:38 UTC, kinke wrote:

On Friday, 18 August 2017 at 12:09:04 UTC, kinke wrote:

On Friday, 18 August 2017 at 09:42:25 UTC, Jack Applegame wrote:

For some reason, the LDC default initializes the structure, even if initialization of all its members is specified as void. I believe that this is wrong.

Afaik, this has been brought up multiple times already and is so by design. Every aggregate has an init symbol, omitting that (and accordingly the default initialization of all instances) by initializing each field with void doesn't work. The initialization isn't performed fieldwise, but is a bitcopy of T.init. You can skip initialization of specific instances though - `S s = void;` - but again not if `s` is a field of another aggregate.

Sorry, I forgot some workaround code:

void ResetHandler() {
    Foo foo = void;
    foo.__ctor(10);
    // or: std.conv.emplace(&foo, 10);
}

Thanks for the answer. Also I found another workaround code:

test.d
****************************************
module test;

import core.bitop : volatileStore;

struct Foo {
        uint[64] m = void; // no default initialization
        static auto opCall(uint a) {
                Foo foo = void;
                foreach(ref b; foo.m) volatileStore(&b,a++);
                return foo;
        }
}

void ResetHandler() {
        auto foo = Foo(10);
}
****************************************

assembly
****************************************
00000000 <_D4test12ResetHandlerFZv>:
   0:   b0c0            sub     sp, #256        ; 0x100
   2:   2000            movs    r0, #0
   4:   4669            mov     r1, sp
   6:   f100 020a       add.w   r2, r0, #10
   a:   f841 2020       str.w   r2, [r1, r0, lsl #2]
   e:   3001            adds    r0, #1
  10:   2a49            cmp     r2, #73 ; 0x49
  12:   d1f8            bne.n   6 <_D4test12ResetHandlerFZv+0x6>
  14:   b040            add     sp, #256        ; 0x100
  16:   4770            bx      lr
****************************************