Core.atomic: Fencing?

[dsimcha]

Are all atomic functions in core.atomic going to be guaranteed to act as full
memory barriers when it's ported to non-x86 architectures?  std.parallelism
assumes that atomic instructions act as full barriers.  This is correct on
x86/x86, since loads and stores cannot be reordered with locked instructions,
and everything in the x86/x64 implementation of core.atomic uses the lock
prefix.  Are similar guarantees going to be made on other architectures?