Specman design Verification Allentown, PA
Duration- 12 months Rate Market *Job Description:* * * • Create high quality test cases and sequences in SystemVerilog UVM/OVM • Assist in verification plan development. • Utilize advanced verification techniques. • Assist with functional coverage development and reporting. • Write tools and scripts in Perl and other script languages to enhance the verification process *Qualifications and requirements*: • BS, MS, PhD, in computer science or engineering • Experience with an OOP language, SystemVerilog is preferred. • PCIE and/or USB experience is highly desired. • UVM or OVM or related methodology is highly desired. • Experience with simulators from the major EDA suppliers (Cadence, Mentor or Synopsys) • Experience with advanced verification techniques like constrained random generation and functional coverage. • Experience with tools for regression management, configuration management and bug tracking • Good software skills in object oriented programming (OOP), C, C++, Perl, csh • Good problem solving and debugging skills Please include the below Required Details . Consultant Full Name: Email Id: Phone/Cell Number : Current Location : Visa Status: Hourly Rate on c2c/w2 all inclusive: Availability: Relocation Yes/No: Thanks, Sam Email [email protected] Phone 732-917-4895 Fax 732-875-0233 SourceChip, Inc 7 Rustic Drive, North Brunswick, NJ – 08902 Visit us www.sourcechip.net -- You received this message because you are subscribed to the Google Groups "Hot List" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send email to [email protected]. Visit this group at http://groups.google.com/group/directclienteq. For more options, visit https://groups.google.com/groups/opt_out.
