Hi,
I found why the overlay wasn't working with Radeon9200 with 128M of memory. The surface manager allocates overlay buffers on top of video memory. But the mask 0x03fffff0 applied to the VID_BUF0_BASE_ADRS, VID_BUF1_BASE_ADRS, VID_BUF2_BASE_ADRS, VID_BUF3_BASE_ADRS, VID_BUF4_BASE_ADRS, VID_BUF5_BASE_ADRS registers did not allow buffer offsets >64M.
The patch fixes this and other errors in the radeon driver. Please, apply.
Regards Vadim Catana, [EMAIL PROTECTED]
===================================================================
diff -urN ./DirectFB/gfxdrivers/radeon/radeon.c
./DirectFB.test/gfxdrivers/radeon/radeon.c
--- ./DirectFB/gfxdrivers/radeon/radeon.c 2004-04-07 18:09:34.000000000 +0300
+++ ./DirectFB.test/gfxdrivers/radeon/radeon.c 2004-04-29 10:03:39.102499384 +0300
@@ -436,6 +436,8 @@
adrv->mmio_base = ( volatile __u8* ) dfb_gfxcard_map_mmio( device, 0, -1 );
if (!adrv->mmio_base)
return DFB_IO;
+
+ adrv->device_data = (RADEONDeviceData*) device_data; /* fill acceleration function table */
funcs->CheckState = radeonCheckState;
diff -urN ./DirectFB/gfxdrivers/radeon/radeon.h
./DirectFB.test/gfxdrivers/radeon/radeon.h
--- ./DirectFB/gfxdrivers/radeon/radeon.h 2004-04-07 18:09:34.000000000 +0300
+++ ./DirectFB.test/gfxdrivers/radeon/radeon.h 2004-04-28 11:23:40.000000000 +0300
@@ -34,10 +34,6 @@
#include <core/layers.h> typedef struct {
- volatile __u8 *mmio_base;
-} RADEONDriverData;
-
-typedef struct {
CoreSurface *source;
CoreSurface *destination;
DFBSurfaceBlittingFlags blittingflags;
@@ -63,6 +59,11 @@
unsigned int fifo_cache_hits;
} RADEONDeviceData;+typedef struct {
+ volatile __u8 *mmio_base;
+ RADEONDeviceData *device_data;
+} RADEONDriverData;
+
extern DisplayLayerFuncs RadeonOverlayFuncs; #endif
diff -urN ./DirectFB/gfxdrivers/radeon/radeon_overlay.c
./DirectFB.test/gfxdrivers/radeon/radeon_overlay.c
--- ./DirectFB/gfxdrivers/radeon/radeon_overlay.c 2004-04-07 18:09:34.000000000
+0300
+++ ./DirectFB.test/gfxdrivers/radeon/radeon_overlay.c 2004-04-29 10:19:44.000000000
+0300
@@ -52,9 +52,13 @@
__u32 P1_X_START_END;
__u32 P2_X_START_END;
__u32 P3_X_START_END;
+ __u32 DISPLAY_BASE_ADDR;
__u32 VID_BUF0_BASE_ADRS;
__u32 VID_BUF1_BASE_ADRS;
__u32 VID_BUF2_BASE_ADRS;
+ __u32 VID_BUF3_BASE_ADRS;
+ __u32 VID_BUF4_BASE_ADRS;
+ __u32 VID_BUF5_BASE_ADRS;
__u32 P1_V_ACCUM_INIT;
__u32 P23_V_ACCUM_INIT;
__u32 P1_H_ACCUM_INIT;
@@ -69,7 +73,7 @@
} regs;
} RadeonOverlayLayerData;-#define OV0_SUPPORTED_OPTIONS (DLOP_DEINTERLACING | DLOP_DST_COLORKEY | DLOP_SRC_COLORKEY | DLOP_OPACITY | DLOP_ALPHACHANNEL) +#define OV0_SUPPORTED_OPTIONS ( DLOP_DST_COLORKEY | DLOP_SRC_COLORKEY | DLOP_OPACITY | DLOP_ALPHACHANNEL)
static void ov_calc_scaler_regs ( @@ -79,20 +83,13 @@ CoreLayerRegionConfig *config ) { - int tmp; - int v_inc; - int h_inc; - int step_by; - int p1_h_accum_init; - int p23_h_accum_init; - int p1_v_accum_init; - int p23_v_accum_init; + __u32 tmp; + __u32 h_inc; + __u32 step_by;
+ h_inc = (surface->width << 12) / config->dest.w;
- v_inc = (surface->height << 20) / config->dest.h;
- h_inc = (surface->width << 12) / config->dest.w;
step_by = 1;
-
while (h_inc >= (2 << 12)) {
step_by++;
h_inc >>= 1;
@@ -100,28 +97,39 @@ /* calculate values for horizontal accumulators */
tmp = 0x00028000 + (h_inc << 3);
- p1_h_accum_init = ((tmp << 4) & 0x000f8000) | ((tmp << 12) & 0xf0000000);
+ rov0->regs.P1_H_ACCUM_INIT = ((tmp << 4) & 0x000f8000) | ((tmp << 12) &
0xf0000000);tmp = 0x00028000 + (h_inc << 2); - p23_h_accum_init = ((tmp << 4) & 0x000f8000) | ((tmp << 12) & 0x70000000); + rov0->regs.P23_H_ACCUM_INIT = ((tmp << 4) & 0x000f8000) | ((tmp << 12) & 0x70000000);
/* calculate values for vertical accumulators */
tmp = 0x00018000;
- p1_v_accum_init = ((tmp << 4) & 0x03ff8000) | 0x00000001;
+ rov0->regs.P1_V_ACCUM_INIT = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) |
(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1);tmp = 0x00018000; - p23_v_accum_init = ((tmp << 4) & 0x01ff8000) | 0x00000001; + rov0->regs.P23_V_ACCUM_INIT = ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) | (OV0_P23_MAX_LN_IN_PER_LN_OUT & 1); +
+ rov0->regs.H_INC = h_inc | ((h_inc >> 1) << 16);
- rov0->regs.V_INC = v_inc;
- rov0->regs.H_INC = h_inc | ((h_inc >> 1) << 16);
rov0->regs.STEP_BY = step_by | (step_by << 8);- rov0->regs.P1_H_ACCUM_INIT = p1_h_accum_init; - rov0->regs.P23_H_ACCUM_INIT = p23_h_accum_init; - rov0->regs.P1_V_ACCUM_INIT = p1_v_accum_init; - rov0->regs.P23_V_ACCUM_INIT = p23_v_accum_init; + rov0->regs.V_INC = (surface->height << 20) / config->dest.h; + + rov0->regs.Y_X_START = (config->dest.x) | (config->dest.y << 16); + rov0->regs.Y_X_END = (config->dest.x + config->dest.w) | ((config->dest.y + config->dest.h) << 16); + + rov0->regs.P1_BLANK_LINES_AT_TOP = P1_BLNK_LN_AT_TOP_M1_MASK | ( (surface->height - 1) << 16); + rov0->regs.P23_BLANK_LINES_AT_TOP = P23_BLNK_LN_AT_TOP_M1_MASK | (( ((surface->height + 1) >> 1) - 1) << 16);
+ rov0->regs.P1_X_START_END = (surface->width - 1); + rov0->regs.P2_X_START_END = ( ( surface->width >> 1 ) - 1 ); + rov0->regs.P3_X_START_END = ( ( surface->width >> 1 ) - 1 ); + + rov0->regs.VID_BUF_PITCH0_VALUE = surface->front_buffer->video.pitch; + rov0->regs.VID_BUF_PITCH1_VALUE = surface->front_buffer->video.pitch >> 1; + + rov0->regs.DISPLAY_BASE_ADDR = radeon_in32( rdrv->mmio_base, DISP_BASE_ADDR); }
static void ov_calc_buffer_regs(
@@ -169,21 +177,35 @@
offset = front_buffer->video.offset;
offset += croptop * front_buffer->video.pitch + cropleft * DFB_BYTES_PER_PIXEL(
surface->format );- rov0->regs.VID_BUF0_BASE_ADRS = offset & 0x03fffff0; - rov0->regs.VID_BUF1_BASE_ADRS = (offset_u & 0x03fffff0) | 1; - rov0->regs.VID_BUF2_BASE_ADRS = (offset_v & 0x03fffff0) | 1; - - rov0->regs.VID_BUF_PITCH0_VALUE = front_buffer->video.pitch; - rov0->regs.VID_BUF_PITCH1_VALUE = front_buffer->video.pitch >> 1; + rov0->regs.VID_BUF0_BASE_ADRS = offset & VIF_BUF0_BASE_ADRS_MASK; + rov0->regs.VID_BUF1_BASE_ADRS = (offset_u & VIF_BUF1_BASE_ADRS_MASK) | VIF_BUF1_PITCH_SEL; + rov0->regs.VID_BUF2_BASE_ADRS = (offset_v & VIF_BUF2_BASE_ADRS_MASK) | VIF_BUF2_PITCH_SEL; + + rov0->regs.VID_BUF3_BASE_ADRS = offset & VIF_BUF3_BASE_ADRS_MASK; + rov0->regs.VID_BUF4_BASE_ADRS = (offset_u & VIF_BUF4_BASE_ADRS_MASK) | VIF_BUF1_PITCH_SEL; + rov0->regs.VID_BUF5_BASE_ADRS = (offset_v & VIF_BUF5_BASE_ADRS_MASK) | VIF_BUF2_PITCH_SEL; +}
+static void ov_set_buffer_regs(
+ RADEONDriverData *rdrv,
+ RadeonOverlayLayerData *rov0,
+ CoreSurface *surface )
+{
+ RADEONDeviceData *rdev = rdrv->device_data;+ radeon_waitfifo(rdrv, rdev, 15);
radeon_out32( rdrv->mmio_base, OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK);
+ radeon_waitidle(rdrv, rdev);
while(!(radeon_in32( rdrv->mmio_base, OV0_REG_LOAD_CNTL) &
REG_LD_CTL_LOCK_READBACK)); radeon_out32( rdrv->mmio_base, OV0_VID_BUF0_BASE_ADRS,
rov0->regs.VID_BUF0_BASE_ADRS );
radeon_out32( rdrv->mmio_base, OV0_VID_BUF1_BASE_ADRS,
rov0->regs.VID_BUF1_BASE_ADRS );
radeon_out32( rdrv->mmio_base, OV0_VID_BUF2_BASE_ADRS,
rov0->regs.VID_BUF2_BASE_ADRS );+ radeon_out32( rdrv->mmio_base, OV0_VID_BUF3_BASE_ADRS,
rov0->regs.VID_BUF3_BASE_ADRS );
+ radeon_out32( rdrv->mmio_base, OV0_VID_BUF4_BASE_ADRS,
rov0->regs.VID_BUF4_BASE_ADRS );
+ radeon_out32( rdrv->mmio_base, OV0_VID_BUF5_BASE_ADRS,
rov0->regs.VID_BUF5_BASE_ADRS );
+
radeon_out32( rdrv->mmio_base, OV0_REG_LOAD_CNTL, 0);
}@@ -298,6 +320,7 @@
CorePalette *palette )
{
RADEONDriverData *rdrv = (RADEONDriverData*) driver_data;
+ RADEONDeviceData *rdev = rdrv->device_data;
RadeonOverlayLayerData *rov0 = (RadeonOverlayLayerData*) layer_data; volatile __u8 *mmio = rdrv->mmio_base;
@@ -307,68 +330,11 @@
/* save configuration */
rov0->config = *config;- /* clear everything except the enable bit */
- rov0->regs.SCALE_CNTL &= SCALER_ENABLE;
-
- rov0->regs.SCALE_CNTL |= SCALER_DOUBLE_BUFFER_REGS | SCALER_BURST_PER_PLANE;
-
- /* set pixel format */
- switch (surface->format) {
- case DSPF_ARGB1555:
- rov0->regs.SCALE_CNTL = SCALER_SOURCE_15BPP;
- break;
-
- case DSPF_RGB16:
- rov0->regs.SCALE_CNTL = SCALER_SOURCE_16BPP;
- break;
-
- case DSPF_RGB32:
- rov0->regs.SCALE_CNTL = SCALER_SOURCE_32BPP;
- break;
-
- case DSPF_UYVY:
- rov0->regs.SCALE_CNTL = SCALER_SOURCE_YVYU422;
- break;
-
- case DSPF_YUY2:
- rov0->regs.SCALE_CNTL = SCALER_SOURCE_VYUY422;
- break;
-
- case DSPF_I420:
- rov0->regs.SCALE_CNTL = SCALER_SOURCE_YUV12;
- break;
-
- case DSPF_YV12:
- rov0->regs.SCALE_CNTL = SCALER_SOURCE_YUV12;
- break;
-
- default:
- D_BUG("unexpected pixelformat");
- rov0->regs.SCALE_CNTL = 0;
- return DFB_UNSUPPORTED;
- }
-
- ov_calc_scaler_regs ( rdrv, rov0, surface, config );
- ov_calc_buffer_regs ( rdrv, rov0, surface );
-
- rov0->regs.Y_X_START = config->dest.x | (config->dest.y << 16);
- rov0->regs.Y_X_END = (config->dest.x + config->dest.w) | ((config->dest.y +
config->dest.h) << 16);
- rov0->regs.P1_BLANK_LINES_AT_TOP = 0x00000fff | ((surface->height - 1) << 16);
- rov0->regs.P23_BLANK_LINES_AT_TOP = 0x000007ff | ((((surface->height + 1) >> 1) - 1)
<< 16);
- rov0->regs.P1_X_START_END = surface->width - 1;
- rov0->regs.P2_X_START_END = (surface->width >> 1) - 1;
- rov0->regs.P3_X_START_END = (surface->width >> 1) - 1;
-
-
/* set graphics and overlay blend mode */
rov0->regs.VID_KEY_CLR_LOW = PIXEL_RGB32( config->src_key.r, config->src_key.g,
config->src_key.b );
rov0->regs.VID_KEY_CLR_HIGH = rov0->regs.VID_KEY_CLR_LOW; switch (primary_format) {
- case DSPF_RGB332:
- rov0->regs.GRPH_KEY_CLR_LOW = PIXEL_RGB332( config->dst_key.r,
config->dst_key.g, config->dst_key.b );
- break;
-
case DSPF_ARGB1555:
rov0->regs.GRPH_KEY_CLR_LOW = PIXEL_ARGB1555( config->dst_key.a,
config->dst_key.r, config->dst_key.g, config->dst_key.b );
break;
@@ -392,12 +358,13 @@rov0->regs.GRPH_KEY_CLR_HIGH = rov0->regs.GRPH_KEY_CLR_LOW;
+
rov0->regs.DISP_MERGE_CONTROL = 0xffff0001;
rov0->regs.KEY_CNTL = 0; if (config->options & DLOP_SRC_COLORKEY) {
rov0->regs.DISP_MERGE_CONTROL = 0xffff0000;
- rov0->regs.KEY_CNTL = VIDEO_KEY_FN_EQ;
+ rov0->regs.KEY_CNTL = VIDEO_KEY_FN_NE;
} if (config->options & DLOP_DST_COLORKEY) {
@@ -415,21 +382,86 @@
rov0->regs.KEY_CNTL = VIDEO_KEY_FN_FALSE | GRAPHIC_KEY_FN_FALSE;
}+
+ ov_calc_scaler_regs ( rdrv, rov0, surface, config );
+ ov_calc_buffer_regs ( rdrv, rov0, surface );
+
+
+ rov0->regs.SCALE_CNTL = SCALER_ENABLE |
+ SCALER_SMART_SWITCH |
+ SCALER_Y2R_TEMP |
+ SCALER_PIX_EXPAND |
+ SCALER_DOUBLE_BUFFER_REGS;
+
+ /* set pixel format */
+ switch (surface->format) {
+ case DSPF_ARGB1555:
+ rov0->regs.SCALE_CNTL |= SCALER_SOURCE_15BPP;
+ break;
+
+ case DSPF_RGB16:
+ rov0->regs.SCALE_CNTL |= SCALER_SOURCE_16BPP;
+ break;
+
+ case DSPF_RGB32:
+ rov0->regs.SCALE_CNTL |= SCALER_SOURCE_32BPP;
+ break;
+
+ case DSPF_UYVY:
+ rov0->regs.SCALE_CNTL |= SCALER_SOURCE_YVYU422;
+ break;
+
+ case DSPF_YUY2:
+ rov0->regs.SCALE_CNTL |= SCALER_SOURCE_VYUY422;
+ break;
+
+ case DSPF_I420:
+ rov0->regs.SCALE_CNTL |= SCALER_SOURCE_YUV12;
+ break;
+
+ case DSPF_YV12:
+ rov0->regs.SCALE_CNTL |= SCALER_SOURCE_YUV12;
+ break;
+
+ default:
+ D_BUG("unexpected pixelformat");
+ rov0->regs.SCALE_CNTL = 0;
+ return DFB_UNSUPPORTED;
+ }
+
+
+ /* reset overlay */
+ radeon_waitidle(rdrv, rdev);
+ radeon_out32( mmio, OV0_SCALE_CNTL, SCALER_SOFT_RESET );
+ radeon_out32( mmio, OV0_EXCLUSIVE_HORZ, 0 );
+ radeon_out32( mmio, OV0_AUTO_FLIP_CNTL, 0 );
+ radeon_out32( mmio, OV0_FILTER_CNTL, FILTER_HARDCODED_COEF );
+ radeon_out32( mmio, OV0_KEY_CNTL, GRAPHIC_KEY_FN_EQ);
+ radeon_out32( mmio, OV0_TEST, 0 );
+
/* set registers */
- radeon_out32( mmio, OV0_REG_LOAD_CNTL, 1 );
- while (!(radeon_in32( mmio, OV0_REG_LOAD_CNTL ) & (1 << 3)));
+ radeon_waitfifo(rdrv, rdev, 2);
+ radeon_out32( mmio, OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK );
+ radeon_waitidle(rdrv, rdev);
+ while (!(radeon_in32( mmio, OV0_REG_LOAD_CNTL ) & REG_LD_CTL_LOCK_READBACK));
+ radeon_waitfifo(rdrv, rdev, 15);
+
+ /* Shutdown capturing */
+ radeon_out32( mmio, FCP_CNTL, FCP_CNTL__GND);
+ radeon_out32( mmio, CAP0_TRIG_CNTL, 0);
+ radeon_out32( mmio, VID_BUFFER_CONTROL, (1<<16) | 0x01);
+ radeon_out32( mmio, DISP_TEST_DEBUG_CNTL, 0);- radeon_out32( mmio, OV0_SCALE_CNTL, 0x80000000 );
- radeon_out32( mmio, OV0_EXCLUSIVE_HORZ, 0 );
- radeon_out32( mmio, OV0_AUTO_FLIP_CNTL, 0 );
- radeon_out32( mmio, OV0_FILTER_CNTL, 0x0000000f );
- radeon_out32( mmio, OV0_TEST, 0 );
+ radeon_out32( mmio, OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD);
+
+ radeon_waitfifo(rdrv, rdev, 2);
radeon_out32( mmio, DISP_MERGE_CNTL, rov0->regs.DISP_MERGE_CONTROL);
radeon_out32( mmio, OV0_VID_KEY_CLR_LOW, rov0->regs.VID_KEY_CLR_LOW);
radeon_out32( mmio, OV0_VID_KEY_CLR_HIGH, rov0->regs.VID_KEY_CLR_HIGH);
radeon_out32( mmio, OV0_GRPH_KEY_CLR_LOW, rov0->regs.GRPH_KEY_CLR_LOW);
radeon_out32( mmio, OV0_GRPH_KEY_CLR_HIGH, rov0->regs.GRPH_KEY_CLR_HIGH);
radeon_out32( mmio, OV0_KEY_CNTL, rov0->regs.KEY_CNTL);
+
radeon_out32( mmio, OV0_H_INC, rov0->regs.H_INC );
radeon_out32( mmio, OV0_STEP_BY, rov0->regs.STEP_BY );
radeon_out32( mmio, OV0_Y_X_START, rov0->regs.Y_X_START );
@@ -442,17 +474,28 @@
radeon_out32( mmio, OV0_P1_X_START_END, rov0->regs.P1_X_START_END );
radeon_out32( mmio, OV0_P2_X_START_END, rov0->regs.P2_X_START_END );
radeon_out32( mmio, OV0_P3_X_START_END, rov0->regs.P3_X_START_END );
+ radeon_out32( mmio, OV0_BASE_ADDR, rov0->regs.DISPLAY_BASE_ADDR);
+
+ radeon_out32( mmio, OV0_VID_BUF0_BASE_ADRS,
rov0->regs.VID_BUF0_BASE_ADRS );
+ radeon_out32( mmio, OV0_VID_BUF1_BASE_ADRS,
rov0->regs.VID_BUF1_BASE_ADRS );
+ radeon_out32( mmio, OV0_VID_BUF2_BASE_ADRS,
rov0->regs.VID_BUF2_BASE_ADRS );
+
+ radeon_waitfifo(rdrv, rdev, 9);
+ radeon_out32( mmio, OV0_VID_BUF3_BASE_ADRS,
rov0->regs.VID_BUF3_BASE_ADRS );
+ radeon_out32( mmio, OV0_VID_BUF4_BASE_ADRS,
rov0->regs.VID_BUF4_BASE_ADRS );
+ radeon_out32( mmio, OV0_VID_BUF5_BASE_ADRS,
rov0->regs.VID_BUF5_BASE_ADRS );
+
radeon_out32( mmio, OV0_P1_V_ACCUM_INIT, rov0->regs.P1_V_ACCUM_INIT );
- radeon_out32( mmio, OV0_P23_V_ACCUM_INIT, rov0->regs.P23_V_ACCUM_INIT );
radeon_out32( mmio, OV0_P1_H_ACCUM_INIT, rov0->regs.P1_H_ACCUM_INIT );
+ radeon_out32( mmio, OV0_P23_V_ACCUM_INIT, rov0->regs.P23_V_ACCUM_INIT );
radeon_out32( mmio, OV0_P23_H_ACCUM_INIT, rov0->regs.P23_H_ACCUM_INIT );- radeon_out32( mmio, OV0_REG_LOAD_CNTL, 0 );
/* enable overlay */
- rov0->regs.SCALE_CNTL |= SCALER_ENABLE;
radeon_out32( mmio, OV0_SCALE_CNTL, rov0->regs.SCALE_CNTL );+ radeon_out32( mmio, OV0_REG_LOAD_CNTL, 0 );
+
return DFB_OK;
}@@ -470,6 +513,7 @@
dfb_surface_flip_buffers( surface );ov_calc_buffer_regs( rdrv, rov0, surface ); + ov_set_buffer_regs( rdrv, rov0, surface );
return DFB_OK; } diff -urN ./DirectFB/gfxdrivers/radeon/radeon_regs.h ./DirectFB.test/gfxdrivers/radeon/radeon_regs.h --- ./DirectFB/gfxdrivers/radeon/radeon_regs.h 2004-04-07 18:09:34.000000000 +0300 +++ ./DirectFB.test/gfxdrivers/radeon/radeon_regs.h 2004-04-29 09:12:42.000000000 +0300 @@ -197,32 +197,32 @@ #define OV0_VID_BUF0_BASE_ADRS 0x0440 # define VIF_BUF0_PITCH_SEL 0x00000001L # define VIF_BUF0_TILE_ADRS 0x00000002L -# define VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF0_BASE_ADRS_MASK 0xfffffff0L # define VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L #define OV0_VID_BUF1_BASE_ADRS 0x0444 # define VIF_BUF1_PITCH_SEL 0x00000001L # define VIF_BUF1_TILE_ADRS 0x00000002L -# define VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF1_BASE_ADRS_MASK 0xfffffff0L # define VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L #define OV0_VID_BUF2_BASE_ADRS 0x0448 # define VIF_BUF2_PITCH_SEL 0x00000001L # define VIF_BUF2_TILE_ADRS 0x00000002L -# define VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF2_BASE_ADRS_MASK 0xfffffff0L # define VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L #define OV0_VID_BUF3_BASE_ADRS 0x044C # define VIF_BUF3_PITCH_SEL 0x00000001L # define VIF_BUF3_TILE_ADRS 0x00000002L -# define VIF_BUF3_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF3_BASE_ADRS_MASK 0xfffffff0L # define VIF_BUF3_1ST_LINE_LSBS_MASK 0x48000000L #define OV0_VID_BUF4_BASE_ADRS 0x0450 # define VIF_BUF4_PITCH_SEL 0x00000001L # define VIF_BUF4_TILE_ADRS 0x00000002L -# define VIF_BUF4_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF4_BASE_ADRS_MASK 0xfffffff0L # define VIF_BUF4_1ST_LINE_LSBS_MASK 0x48000000L #define OV0_VID_BUF5_BASE_ADRS 0x0454 # define VIF_BUF5_PITCH_SEL 0x00000001L # define VIF_BUF5_TILE_ADRS 0x00000002L -# define VIF_BUF5_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF5_BASE_ADRS_MASK 0xfffffff0L # define VIF_BUF5_1ST_LINE_LSBS_MASK 0x48000000L #define OV0_VID_BUF_PITCH0_VALUE 0x0460 #define OV0_VID_BUF_PITCH1_VALUE 0x0464 @@ -319,5 +319,19 @@ #define OV0_LIN_TRANS_F 0x0D34
#define DISP_MERGE_CNTL 0x0D60 +#define DISP_TEST_DEBUG_CNTL 0x0D10 +#define DISP_BASE_ADDR 0x023C + +#define VID_BUFFER_CONTROL 0x0900 + +#define FCP_CNTL 0x0910 +# define FCP_CNTL__PCICLK 0 +# define FCP_CNTL__PCLK 1 +# define FCP_CNTL__PCLKb 2 +# define FCP_CNTL__HREF 3 +# define FCP_CNTL__GND 4 +# define FCP_CNTL__HREFb 5 + +#define CAP0_TRIG_CNTL 0x0950
#endif
diff -urN ./DirectFB/gfxdrivers/radeon/radeon.c
./DirectFB.test/gfxdrivers/radeon/radeon.c
--- ./DirectFB/gfxdrivers/radeon/radeon.c 2004-04-07 18:09:34.000000000 +0300
+++ ./DirectFB.test/gfxdrivers/radeon/radeon.c 2004-04-29 10:03:39.102499384 +0300
@@ -436,6 +436,8 @@
adrv->mmio_base = ( volatile __u8* ) dfb_gfxcard_map_mmio( device, 0, -1 );
if (!adrv->mmio_base)
return DFB_IO;
+
+ adrv->device_data = (RADEONDeviceData*) device_data;
/* fill acceleration function table */
funcs->CheckState = radeonCheckState;
diff -urN ./DirectFB/gfxdrivers/radeon/radeon.h
./DirectFB.test/gfxdrivers/radeon/radeon.h
--- ./DirectFB/gfxdrivers/radeon/radeon.h 2004-04-07 18:09:34.000000000 +0300
+++ ./DirectFB.test/gfxdrivers/radeon/radeon.h 2004-04-28 11:23:40.000000000 +0300
@@ -34,10 +34,6 @@
#include <core/layers.h>
typedef struct {
- volatile __u8 *mmio_base;
-} RADEONDriverData;
-
-typedef struct {
CoreSurface *source;
CoreSurface *destination;
DFBSurfaceBlittingFlags blittingflags;
@@ -63,6 +59,11 @@
unsigned int fifo_cache_hits;
} RADEONDeviceData;
+typedef struct {
+ volatile __u8 *mmio_base;
+ RADEONDeviceData *device_data;
+} RADEONDriverData;
+
extern DisplayLayerFuncs RadeonOverlayFuncs;
#endif
diff -urN ./DirectFB/gfxdrivers/radeon/radeon_overlay.c
./DirectFB.test/gfxdrivers/radeon/radeon_overlay.c
--- ./DirectFB/gfxdrivers/radeon/radeon_overlay.c 2004-04-07 18:09:34.000000000
+0300
+++ ./DirectFB.test/gfxdrivers/radeon/radeon_overlay.c 2004-04-29 10:19:44.000000000
+0300
@@ -52,9 +52,13 @@
__u32 P1_X_START_END;
__u32 P2_X_START_END;
__u32 P3_X_START_END;
+ __u32 DISPLAY_BASE_ADDR;
__u32 VID_BUF0_BASE_ADRS;
__u32 VID_BUF1_BASE_ADRS;
__u32 VID_BUF2_BASE_ADRS;
+ __u32 VID_BUF3_BASE_ADRS;
+ __u32 VID_BUF4_BASE_ADRS;
+ __u32 VID_BUF5_BASE_ADRS;
__u32 P1_V_ACCUM_INIT;
__u32 P23_V_ACCUM_INIT;
__u32 P1_H_ACCUM_INIT;
@@ -69,7 +73,7 @@
} regs;
} RadeonOverlayLayerData;
-#define OV0_SUPPORTED_OPTIONS (DLOP_DEINTERLACING | DLOP_DST_COLORKEY |
DLOP_SRC_COLORKEY | DLOP_OPACITY | DLOP_ALPHACHANNEL)
+#define OV0_SUPPORTED_OPTIONS ( DLOP_DST_COLORKEY | DLOP_SRC_COLORKEY | DLOP_OPACITY
| DLOP_ALPHACHANNEL)
static void ov_calc_scaler_regs (
@@ -79,20 +83,13 @@
CoreLayerRegionConfig *config
)
{
- int tmp;
- int v_inc;
- int h_inc;
- int step_by;
- int p1_h_accum_init;
- int p23_h_accum_init;
- int p1_v_accum_init;
- int p23_v_accum_init;
+ __u32 tmp;
+ __u32 h_inc;
+ __u32 step_by;
+ h_inc = (surface->width << 12) / config->dest.w;
- v_inc = (surface->height << 20) / config->dest.h;
- h_inc = (surface->width << 12) / config->dest.w;
step_by = 1;
-
while (h_inc >= (2 << 12)) {
step_by++;
h_inc >>= 1;
@@ -100,28 +97,39 @@
/* calculate values for horizontal accumulators */
tmp = 0x00028000 + (h_inc << 3);
- p1_h_accum_init = ((tmp << 4) & 0x000f8000) | ((tmp << 12) & 0xf0000000);
+ rov0->regs.P1_H_ACCUM_INIT = ((tmp << 4) & 0x000f8000) | ((tmp << 12) &
0xf0000000);
tmp = 0x00028000 + (h_inc << 2);
- p23_h_accum_init = ((tmp << 4) & 0x000f8000) | ((tmp << 12) & 0x70000000);
+ rov0->regs.P23_H_ACCUM_INIT = ((tmp << 4) & 0x000f8000) | ((tmp << 12) &
0x70000000);
/* calculate values for vertical accumulators */
tmp = 0x00018000;
- p1_v_accum_init = ((tmp << 4) & 0x03ff8000) | 0x00000001;
+ rov0->regs.P1_V_ACCUM_INIT = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) |
(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1);
tmp = 0x00018000;
- p23_v_accum_init = ((tmp << 4) & 0x01ff8000) | 0x00000001;
+ rov0->regs.P23_V_ACCUM_INIT = ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) |
(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1);
+
+ rov0->regs.H_INC = h_inc | ((h_inc >> 1) << 16);
- rov0->regs.V_INC = v_inc;
- rov0->regs.H_INC = h_inc | ((h_inc >> 1) << 16);
rov0->regs.STEP_BY = step_by | (step_by << 8);
- rov0->regs.P1_H_ACCUM_INIT = p1_h_accum_init;
- rov0->regs.P23_H_ACCUM_INIT = p23_h_accum_init;
- rov0->regs.P1_V_ACCUM_INIT = p1_v_accum_init;
- rov0->regs.P23_V_ACCUM_INIT = p23_v_accum_init;
+ rov0->regs.V_INC = (surface->height << 20) / config->dest.h;
+
+ rov0->regs.Y_X_START = (config->dest.x) | (config->dest.y << 16);
+ rov0->regs.Y_X_END = (config->dest.x + config->dest.w) | ((config->dest.y +
config->dest.h) << 16);
+
+ rov0->regs.P1_BLANK_LINES_AT_TOP = P1_BLNK_LN_AT_TOP_M1_MASK | (
(surface->height - 1) << 16);
+ rov0->regs.P23_BLANK_LINES_AT_TOP = P23_BLNK_LN_AT_TOP_M1_MASK | ((
((surface->height + 1) >> 1) - 1) << 16);
+ rov0->regs.P1_X_START_END = (surface->width - 1);
+ rov0->regs.P2_X_START_END = ( ( surface->width >> 1 ) - 1 );
+ rov0->regs.P3_X_START_END = ( ( surface->width >> 1 ) - 1 );
+
+ rov0->regs.VID_BUF_PITCH0_VALUE = surface->front_buffer->video.pitch;
+ rov0->regs.VID_BUF_PITCH1_VALUE = surface->front_buffer->video.pitch >> 1;
+
+ rov0->regs.DISPLAY_BASE_ADDR = radeon_in32( rdrv->mmio_base, DISP_BASE_ADDR);
}
static void ov_calc_buffer_regs(
@@ -169,21 +177,35 @@
offset = front_buffer->video.offset;
offset += croptop * front_buffer->video.pitch + cropleft * DFB_BYTES_PER_PIXEL(
surface->format );
- rov0->regs.VID_BUF0_BASE_ADRS = offset & 0x03fffff0;
- rov0->regs.VID_BUF1_BASE_ADRS = (offset_u & 0x03fffff0) | 1;
- rov0->regs.VID_BUF2_BASE_ADRS = (offset_v & 0x03fffff0) | 1;
-
- rov0->regs.VID_BUF_PITCH0_VALUE = front_buffer->video.pitch;
- rov0->regs.VID_BUF_PITCH1_VALUE = front_buffer->video.pitch >> 1;
+ rov0->regs.VID_BUF0_BASE_ADRS = offset & VIF_BUF0_BASE_ADRS_MASK;
+ rov0->regs.VID_BUF1_BASE_ADRS = (offset_u & VIF_BUF1_BASE_ADRS_MASK) |
VIF_BUF1_PITCH_SEL;
+ rov0->regs.VID_BUF2_BASE_ADRS = (offset_v & VIF_BUF2_BASE_ADRS_MASK) |
VIF_BUF2_PITCH_SEL;
+
+ rov0->regs.VID_BUF3_BASE_ADRS = offset & VIF_BUF3_BASE_ADRS_MASK;
+ rov0->regs.VID_BUF4_BASE_ADRS = (offset_u & VIF_BUF4_BASE_ADRS_MASK) |
VIF_BUF1_PITCH_SEL;
+ rov0->regs.VID_BUF5_BASE_ADRS = (offset_v & VIF_BUF5_BASE_ADRS_MASK) |
VIF_BUF2_PITCH_SEL;
+}
+static void ov_set_buffer_regs(
+ RADEONDriverData *rdrv,
+ RadeonOverlayLayerData *rov0,
+ CoreSurface *surface )
+{
+ RADEONDeviceData *rdev = rdrv->device_data;
+ radeon_waitfifo(rdrv, rdev, 15);
radeon_out32( rdrv->mmio_base, OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK);
+ radeon_waitidle(rdrv, rdev);
while(!(radeon_in32( rdrv->mmio_base, OV0_REG_LOAD_CNTL) &
REG_LD_CTL_LOCK_READBACK));
radeon_out32( rdrv->mmio_base, OV0_VID_BUF0_BASE_ADRS,
rov0->regs.VID_BUF0_BASE_ADRS );
radeon_out32( rdrv->mmio_base, OV0_VID_BUF1_BASE_ADRS,
rov0->regs.VID_BUF1_BASE_ADRS );
radeon_out32( rdrv->mmio_base, OV0_VID_BUF2_BASE_ADRS,
rov0->regs.VID_BUF2_BASE_ADRS );
+ radeon_out32( rdrv->mmio_base, OV0_VID_BUF3_BASE_ADRS,
rov0->regs.VID_BUF3_BASE_ADRS );
+ radeon_out32( rdrv->mmio_base, OV0_VID_BUF4_BASE_ADRS,
rov0->regs.VID_BUF4_BASE_ADRS );
+ radeon_out32( rdrv->mmio_base, OV0_VID_BUF5_BASE_ADRS,
rov0->regs.VID_BUF5_BASE_ADRS );
+
radeon_out32( rdrv->mmio_base, OV0_REG_LOAD_CNTL, 0);
}
@@ -298,6 +320,7 @@
CorePalette *palette )
{
RADEONDriverData *rdrv = (RADEONDriverData*) driver_data;
+ RADEONDeviceData *rdev = rdrv->device_data;
RadeonOverlayLayerData *rov0 = (RadeonOverlayLayerData*) layer_data;
volatile __u8 *mmio = rdrv->mmio_base;
@@ -307,68 +330,11 @@
/* save configuration */
rov0->config = *config;
- /* clear everything except the enable bit */
- rov0->regs.SCALE_CNTL &= SCALER_ENABLE;
-
- rov0->regs.SCALE_CNTL |= SCALER_DOUBLE_BUFFER_REGS | SCALER_BURST_PER_PLANE;
-
- /* set pixel format */
- switch (surface->format) {
- case DSPF_ARGB1555:
- rov0->regs.SCALE_CNTL = SCALER_SOURCE_15BPP;
- break;
-
- case DSPF_RGB16:
- rov0->regs.SCALE_CNTL = SCALER_SOURCE_16BPP;
- break;
-
- case DSPF_RGB32:
- rov0->regs.SCALE_CNTL = SCALER_SOURCE_32BPP;
- break;
-
- case DSPF_UYVY:
- rov0->regs.SCALE_CNTL = SCALER_SOURCE_YVYU422;
- break;
-
- case DSPF_YUY2:
- rov0->regs.SCALE_CNTL = SCALER_SOURCE_VYUY422;
- break;
-
- case DSPF_I420:
- rov0->regs.SCALE_CNTL = SCALER_SOURCE_YUV12;
- break;
-
- case DSPF_YV12:
- rov0->regs.SCALE_CNTL = SCALER_SOURCE_YUV12;
- break;
-
- default:
- D_BUG("unexpected pixelformat");
- rov0->regs.SCALE_CNTL = 0;
- return DFB_UNSUPPORTED;
- }
-
- ov_calc_scaler_regs ( rdrv, rov0, surface, config );
- ov_calc_buffer_regs ( rdrv, rov0, surface );
-
- rov0->regs.Y_X_START = config->dest.x | (config->dest.y << 16);
- rov0->regs.Y_X_END = (config->dest.x + config->dest.w) |
((config->dest.y + config->dest.h) << 16);
- rov0->regs.P1_BLANK_LINES_AT_TOP = 0x00000fff | ((surface->height - 1) << 16);
- rov0->regs.P23_BLANK_LINES_AT_TOP = 0x000007ff | ((((surface->height + 1) >> 1) -
1) << 16);
- rov0->regs.P1_X_START_END = surface->width - 1;
- rov0->regs.P2_X_START_END = (surface->width >> 1) - 1;
- rov0->regs.P3_X_START_END = (surface->width >> 1) - 1;
-
-
/* set graphics and overlay blend mode */
rov0->regs.VID_KEY_CLR_LOW = PIXEL_RGB32( config->src_key.r, config->src_key.g,
config->src_key.b );
rov0->regs.VID_KEY_CLR_HIGH = rov0->regs.VID_KEY_CLR_LOW;
switch (primary_format) {
- case DSPF_RGB332:
- rov0->regs.GRPH_KEY_CLR_LOW = PIXEL_RGB332( config->dst_key.r,
config->dst_key.g, config->dst_key.b );
- break;
-
case DSPF_ARGB1555:
rov0->regs.GRPH_KEY_CLR_LOW = PIXEL_ARGB1555( config->dst_key.a,
config->dst_key.r, config->dst_key.g, config->dst_key.b );
break;
@@ -392,12 +358,13 @@
rov0->regs.GRPH_KEY_CLR_HIGH = rov0->regs.GRPH_KEY_CLR_LOW;
+
rov0->regs.DISP_MERGE_CONTROL = 0xffff0001;
rov0->regs.KEY_CNTL = 0;
if (config->options & DLOP_SRC_COLORKEY) {
rov0->regs.DISP_MERGE_CONTROL = 0xffff0000;
- rov0->regs.KEY_CNTL = VIDEO_KEY_FN_EQ;
+ rov0->regs.KEY_CNTL = VIDEO_KEY_FN_NE;
}
if (config->options & DLOP_DST_COLORKEY) {
@@ -415,21 +382,86 @@
rov0->regs.KEY_CNTL = VIDEO_KEY_FN_FALSE | GRAPHIC_KEY_FN_FALSE;
}
+
+ ov_calc_scaler_regs ( rdrv, rov0, surface, config );
+ ov_calc_buffer_regs ( rdrv, rov0, surface );
+
+
+ rov0->regs.SCALE_CNTL = SCALER_ENABLE |
+ SCALER_SMART_SWITCH |
+ SCALER_Y2R_TEMP |
+ SCALER_PIX_EXPAND |
+ SCALER_DOUBLE_BUFFER_REGS;
+
+ /* set pixel format */
+ switch (surface->format) {
+ case DSPF_ARGB1555:
+ rov0->regs.SCALE_CNTL |= SCALER_SOURCE_15BPP;
+ break;
+
+ case DSPF_RGB16:
+ rov0->regs.SCALE_CNTL |= SCALER_SOURCE_16BPP;
+ break;
+
+ case DSPF_RGB32:
+ rov0->regs.SCALE_CNTL |= SCALER_SOURCE_32BPP;
+ break;
+
+ case DSPF_UYVY:
+ rov0->regs.SCALE_CNTL |= SCALER_SOURCE_YVYU422;
+ break;
+
+ case DSPF_YUY2:
+ rov0->regs.SCALE_CNTL |= SCALER_SOURCE_VYUY422;
+ break;
+
+ case DSPF_I420:
+ rov0->regs.SCALE_CNTL |= SCALER_SOURCE_YUV12;
+ break;
+
+ case DSPF_YV12:
+ rov0->regs.SCALE_CNTL |= SCALER_SOURCE_YUV12;
+ break;
+
+ default:
+ D_BUG("unexpected pixelformat");
+ rov0->regs.SCALE_CNTL = 0;
+ return DFB_UNSUPPORTED;
+ }
+
+
+ /* reset overlay */
+ radeon_waitidle(rdrv, rdev);
+ radeon_out32( mmio, OV0_SCALE_CNTL, SCALER_SOFT_RESET );
+ radeon_out32( mmio, OV0_EXCLUSIVE_HORZ, 0 );
+ radeon_out32( mmio, OV0_AUTO_FLIP_CNTL, 0 );
+ radeon_out32( mmio, OV0_FILTER_CNTL, FILTER_HARDCODED_COEF );
+ radeon_out32( mmio, OV0_KEY_CNTL, GRAPHIC_KEY_FN_EQ);
+ radeon_out32( mmio, OV0_TEST, 0 );
+
/* set registers */
- radeon_out32( mmio, OV0_REG_LOAD_CNTL, 1 );
- while (!(radeon_in32( mmio, OV0_REG_LOAD_CNTL ) & (1 << 3)));
+ radeon_waitfifo(rdrv, rdev, 2);
+ radeon_out32( mmio, OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK );
+ radeon_waitidle(rdrv, rdev);
+ while (!(radeon_in32( mmio, OV0_REG_LOAD_CNTL ) & REG_LD_CTL_LOCK_READBACK));
+ radeon_waitfifo(rdrv, rdev, 15);
+
+ /* Shutdown capturing */
+ radeon_out32( mmio, FCP_CNTL, FCP_CNTL__GND);
+ radeon_out32( mmio, CAP0_TRIG_CNTL, 0);
+ radeon_out32( mmio, VID_BUFFER_CONTROL, (1<<16) | 0x01);
+ radeon_out32( mmio, DISP_TEST_DEBUG_CNTL, 0);
- radeon_out32( mmio, OV0_SCALE_CNTL, 0x80000000 );
- radeon_out32( mmio, OV0_EXCLUSIVE_HORZ, 0 );
- radeon_out32( mmio, OV0_AUTO_FLIP_CNTL, 0 );
- radeon_out32( mmio, OV0_FILTER_CNTL, 0x0000000f );
- radeon_out32( mmio, OV0_TEST, 0 );
+ radeon_out32( mmio, OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD);
+
+ radeon_waitfifo(rdrv, rdev, 2);
radeon_out32( mmio, DISP_MERGE_CNTL, rov0->regs.DISP_MERGE_CONTROL);
radeon_out32( mmio, OV0_VID_KEY_CLR_LOW, rov0->regs.VID_KEY_CLR_LOW);
radeon_out32( mmio, OV0_VID_KEY_CLR_HIGH, rov0->regs.VID_KEY_CLR_HIGH);
radeon_out32( mmio, OV0_GRPH_KEY_CLR_LOW, rov0->regs.GRPH_KEY_CLR_LOW);
radeon_out32( mmio, OV0_GRPH_KEY_CLR_HIGH, rov0->regs.GRPH_KEY_CLR_HIGH);
radeon_out32( mmio, OV0_KEY_CNTL, rov0->regs.KEY_CNTL);
+
radeon_out32( mmio, OV0_H_INC, rov0->regs.H_INC );
radeon_out32( mmio, OV0_STEP_BY, rov0->regs.STEP_BY );
radeon_out32( mmio, OV0_Y_X_START, rov0->regs.Y_X_START );
@@ -442,17 +474,28 @@
radeon_out32( mmio, OV0_P1_X_START_END, rov0->regs.P1_X_START_END );
radeon_out32( mmio, OV0_P2_X_START_END, rov0->regs.P2_X_START_END );
radeon_out32( mmio, OV0_P3_X_START_END, rov0->regs.P3_X_START_END );
+ radeon_out32( mmio, OV0_BASE_ADDR, rov0->regs.DISPLAY_BASE_ADDR);
+
+ radeon_out32( mmio, OV0_VID_BUF0_BASE_ADRS,
rov0->regs.VID_BUF0_BASE_ADRS );
+ radeon_out32( mmio, OV0_VID_BUF1_BASE_ADRS,
rov0->regs.VID_BUF1_BASE_ADRS );
+ radeon_out32( mmio, OV0_VID_BUF2_BASE_ADRS,
rov0->regs.VID_BUF2_BASE_ADRS );
+
+ radeon_waitfifo(rdrv, rdev, 9);
+ radeon_out32( mmio, OV0_VID_BUF3_BASE_ADRS,
rov0->regs.VID_BUF3_BASE_ADRS );
+ radeon_out32( mmio, OV0_VID_BUF4_BASE_ADRS,
rov0->regs.VID_BUF4_BASE_ADRS );
+ radeon_out32( mmio, OV0_VID_BUF5_BASE_ADRS,
rov0->regs.VID_BUF5_BASE_ADRS );
+
radeon_out32( mmio, OV0_P1_V_ACCUM_INIT, rov0->regs.P1_V_ACCUM_INIT );
- radeon_out32( mmio, OV0_P23_V_ACCUM_INIT, rov0->regs.P23_V_ACCUM_INIT );
radeon_out32( mmio, OV0_P1_H_ACCUM_INIT, rov0->regs.P1_H_ACCUM_INIT );
+ radeon_out32( mmio, OV0_P23_V_ACCUM_INIT, rov0->regs.P23_V_ACCUM_INIT );
radeon_out32( mmio, OV0_P23_H_ACCUM_INIT, rov0->regs.P23_H_ACCUM_INIT );
- radeon_out32( mmio, OV0_REG_LOAD_CNTL, 0 );
/* enable overlay */
- rov0->regs.SCALE_CNTL |= SCALER_ENABLE;
radeon_out32( mmio, OV0_SCALE_CNTL, rov0->regs.SCALE_CNTL );
+ radeon_out32( mmio, OV0_REG_LOAD_CNTL, 0 );
+
return DFB_OK;
}
@@ -470,6 +513,7 @@
dfb_surface_flip_buffers( surface );
ov_calc_buffer_regs( rdrv, rov0, surface );
+ ov_set_buffer_regs( rdrv, rov0, surface );
return DFB_OK;
}
diff -urN ./DirectFB/gfxdrivers/radeon/radeon_regs.h
./DirectFB.test/gfxdrivers/radeon/radeon_regs.h
--- ./DirectFB/gfxdrivers/radeon/radeon_regs.h 2004-04-07 18:09:34.000000000 +0300
+++ ./DirectFB.test/gfxdrivers/radeon/radeon_regs.h 2004-04-29 09:12:42.000000000
+0300
@@ -197,32 +197,32 @@
#define OV0_VID_BUF0_BASE_ADRS 0x0440
# define VIF_BUF0_PITCH_SEL 0x00000001L
# define VIF_BUF0_TILE_ADRS 0x00000002L
-# define VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L
+# define VIF_BUF0_BASE_ADRS_MASK 0xfffffff0L
# define VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L
#define OV0_VID_BUF1_BASE_ADRS 0x0444
# define VIF_BUF1_PITCH_SEL 0x00000001L
# define VIF_BUF1_TILE_ADRS 0x00000002L
-# define VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L
+# define VIF_BUF1_BASE_ADRS_MASK 0xfffffff0L
# define VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L
#define OV0_VID_BUF2_BASE_ADRS 0x0448
# define VIF_BUF2_PITCH_SEL 0x00000001L
# define VIF_BUF2_TILE_ADRS 0x00000002L
-# define VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L
+# define VIF_BUF2_BASE_ADRS_MASK 0xfffffff0L
# define VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L
#define OV0_VID_BUF3_BASE_ADRS 0x044C
# define VIF_BUF3_PITCH_SEL 0x00000001L
# define VIF_BUF3_TILE_ADRS 0x00000002L
-# define VIF_BUF3_BASE_ADRS_MASK 0x03fffff0L
+# define VIF_BUF3_BASE_ADRS_MASK 0xfffffff0L
# define VIF_BUF3_1ST_LINE_LSBS_MASK 0x48000000L
#define OV0_VID_BUF4_BASE_ADRS 0x0450
# define VIF_BUF4_PITCH_SEL 0x00000001L
# define VIF_BUF4_TILE_ADRS 0x00000002L
-# define VIF_BUF4_BASE_ADRS_MASK 0x03fffff0L
+# define VIF_BUF4_BASE_ADRS_MASK 0xfffffff0L
# define VIF_BUF4_1ST_LINE_LSBS_MASK 0x48000000L
#define OV0_VID_BUF5_BASE_ADRS 0x0454
# define VIF_BUF5_PITCH_SEL 0x00000001L
# define VIF_BUF5_TILE_ADRS 0x00000002L
-# define VIF_BUF5_BASE_ADRS_MASK 0x03fffff0L
+# define VIF_BUF5_BASE_ADRS_MASK 0xfffffff0L
# define VIF_BUF5_1ST_LINE_LSBS_MASK 0x48000000L
#define OV0_VID_BUF_PITCH0_VALUE 0x0460
#define OV0_VID_BUF_PITCH1_VALUE 0x0464
@@ -319,5 +319,19 @@
#define OV0_LIN_TRANS_F 0x0D34
#define DISP_MERGE_CNTL 0x0D60
+#define DISP_TEST_DEBUG_CNTL 0x0D10
+#define DISP_BASE_ADDR 0x023C
+
+#define VID_BUFFER_CONTROL 0x0900
+
+#define FCP_CNTL 0x0910
+# define FCP_CNTL__PCICLK 0
+# define FCP_CNTL__PCLK 1
+# define FCP_CNTL__PCLKb 2
+# define FCP_CNTL__HREF 3
+# define FCP_CNTL__GND 4
+# define FCP_CNTL__HREFb 5
+
+#define CAP0_TRIG_CNTL 0x0950
#endif
