diff -urpN -X dontdiff DirectFB-0.9.20-clean/gfxdrivers/radeon/Makefile.am DirectFB-0.9.20/gfxdrivers/radeon/Makefile.am --- DirectFB-0.9.20-clean/gfxdrivers/radeon/Makefile.am 2003-07-12 10:34:09.000000000 -0700 +++ DirectFB-0.9.20/gfxdrivers/radeon/Makefile.am 2004-04-05 17:40:45.000000000 -0700 @@ -14,7 +14,8 @@ libdirectfb_radeon_la_SOURCES = \ radeon_state.c \ radeon_state.h \ radeon_regs.h \ - radeon_mmio.h + radeon_mmio.h \ + radeon_overlay.c libdirectfb_radeon_la_LDFLAGS = \ -export-dynamic \ diff -urpN -X dontdiff DirectFB-0.9.20-clean/gfxdrivers/radeon/radeon.c DirectFB-0.9.20/gfxdrivers/radeon/radeon.c --- DirectFB-0.9.20-clean/gfxdrivers/radeon/radeon.c 2003-09-23 15:02:30.000000000 -0700 +++ DirectFB-0.9.20/gfxdrivers/radeon/radeon.c 2004-05-27 03:27:28.470225744 -0700 @@ -101,6 +101,12 @@ static void radeonCheckState( void *drv, CardState *state, DFBAccelerationMask accel ) { switch ( state->destination->format ) { + case DSPF_I420: + case DSPF_YV12: + if (!DFB_BLITTING_FUNCTION( accel ) || + (state->source->format != DSPF_I420 && + state->source->format != DSPF_YV12)) + return; case DSPF_RGB332: case DSPF_ARGB1555: case DSPF_RGB16: @@ -129,14 +135,22 @@ static void radeonCheckState( void *drv, && state->source->height >= 8 ) { switch ( state->source->format ) { + case DSPF_I420: + case DSPF_YV12: + if (state->destination->format == DSPF_I420 || + state->destination->format == DSPF_YV12) + state->accel |= RADEON_SUPPORTED_BLITTINGFUNCTIONS; + break; case DSPF_RGB332: case DSPF_ARGB1555: case DSPF_RGB16: case DSPF_RGB32: case DSPF_ARGB: - state->accel |= RADEON_SUPPORTED_BLITTINGFUNCTIONS; + if ( state->source->format == state->destination->format ) + state->accel |= RADEON_SUPPORTED_BLITTINGFUNCTIONS; + /* fall through */ default: - ; + break; } } } @@ -188,8 +202,10 @@ static void radeonSetState( void *drv, v break; } - if ( state->modified & SMF_CLIP ) + if ( state->modified & SMF_CLIP ) { radeon_set_clip( adrv, adev, state ); + adev->clip = state->clip; + } state->modified = 0; } @@ -253,7 +269,9 @@ static bool radeonDrawLine( void *drv, v return true; } -static bool radeonBlit( void *drv, void *dev, DFBRectangle *rect, int dx, int dy ) +static bool radeonDoBlit( void *drv, void *dev, + int x, int y, int w, int h, + int dx, int dy ) { RADEONDriverData *adrv = ( RADEONDriverData* ) drv; RADEONDeviceData *adev = ( RADEONDeviceData* ) dev; @@ -261,23 +279,19 @@ static bool radeonBlit( void *drv, void __u32 dir_cmd = 0; - if ( adev->source->format != adev->destination->format ) { - BUG( "blitting source/destination format mismatch" ); - } - /* check which blitting direction should be used */ - if ( rect->x <= dx ) { + if ( x <= dx ) { dir_cmd |= DST_X_RIGHT_TO_LEFT; - rect->x += rect->w-1; - dx += rect->w-1; + x += w-1; + dx += w-1; } else { dir_cmd |= DST_X_LEFT_TO_RIGHT; } - if ( rect->y <= dy ) { + if ( y <= dy ) { dir_cmd |= DST_Y_BOTTOM_TO_TOP; - rect->y += rect->h-1; - dy += rect->h-1; + y += h-1; + dy += h-1; } else { dir_cmd |= DST_Y_TOP_TO_BOTTOM; } @@ -288,13 +302,118 @@ static bool radeonBlit( void *drv, void radeon_out32( mmio, DP_CNTL, dir_cmd ); /* set coordinates and initiate blit */ - radeon_out32( mmio, SRC_Y_X, ( rect->y << 16 ) | S14( rect->x ) ); + radeon_out32( mmio, SRC_Y_X, ( y << 16 ) | S14( x ) ); radeon_out32( mmio, DST_Y_X, ( dy << 16 ) | S14( dx ) ); - radeon_out32( mmio, DST_HEIGHT_WIDTH, ( rect->h << 16 ) | S14( rect->w ) ); + radeon_out32( mmio, DST_HEIGHT_WIDTH, ( h << 16 ) | S14( w ) ); return true; } +static bool radeonBlit( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ) +{ + RADEONDriverData *adrv = ( RADEONDriverData* ) drv; + RADEONDeviceData *adev = ( RADEONDeviceData* ) dev; + volatile __u8 *mmio = adrv->mmio_base; + + DFBRegion clip; + SurfaceBuffer *src_buffer = adev->source->front_buffer; + SurfaceBuffer *dst_buffer = adev->destination->back_buffer; + __u32 src_offset_u, src_offset_v, src_pitch; + __u32 dst_offset_u, dst_offset_v, dst_pitch; + + radeonDoBlit( adrv, adev, rect->x, rect->y, rect->w, rect->h, dx, dy ); + + switch (adev->source->format) { + case DSPF_I420: + src_offset_u = src_buffer->video.offset + + adev->source->height * src_buffer->video.pitch; + src_offset_v = src_offset_u + + (adev->source->height >> 1) * (src_buffer->video.pitch >> 1); + src_pitch = src_buffer->video.pitch/2; + break; + case DSPF_YV12: + src_offset_v = src_buffer->video.offset + + adev->source->height * src_buffer->video.pitch; + src_offset_u = src_offset_v + + (adev->source->height >> 1) * (src_buffer->video.pitch >> 1); + src_pitch = src_buffer->video.pitch/2; + break; + default: + return true; + } + + switch (adev->destination->format) { + case DSPF_I420: + dst_offset_u = dst_buffer->video.offset + + adev->destination->height * dst_buffer->video.pitch; + dst_offset_v = dst_offset_u + + (adev->destination->height >> 1) * (dst_buffer->video.pitch >> 1); + dst_pitch = dst_buffer->video.pitch/2; + break; + case DSPF_YV12: + dst_offset_v = dst_buffer->video.offset + + adev->destination->height * dst_buffer->video.pitch; + dst_offset_u = dst_offset_v + + (adev->destination->height >> 1) * (dst_buffer->video.pitch >> 1); + dst_pitch = dst_buffer->video.pitch/2; + break; + default: + BUG( "blitting source/destination format mismatch" ); + return false; + } + + rect->x /= 2; rect->y /= 2; + rect->w /= 2; rect->h /= 2; + dx /= 2; dy /= 2; + + clip.x1 = adev->clip.x1 / 2; + clip.x2 = adev->clip.x2 / 2; + clip.y1 = adev->clip.y1 / 2; + clip.y2 = adev->clip.y2 / 2; + + /* u plane */ + radeon_waitfifo( adrv, adev, 6 ); + radeon_out32( mmio, DST_PITCH, dst_pitch ); + radeon_out32( mmio, DST_OFFSET, + adev->RADEON_display_base_addr + dst_offset_u ); + radeon_out32( mmio, SRC_PITCH, src_pitch ); + radeon_out32( mmio, SRC_OFFSET, + adev->RADEON_display_base_addr + src_offset_u ); + radeon_out32( mmio, SC_TOP_LEFT, (clip.y1 << 16) | (clip.x1) ); + radeon_out32( mmio, SC_BOTTOM_RIGHT, + ((clip.y2 + 1) << 16) | (clip.x2 + 1) ); + + radeonDoBlit( adrv, adev, rect->x, rect->y, rect->w, rect->h, dx, dy ); + + /* v plane */ + radeon_waitfifo( adrv, adev, 6 ); + radeon_out32( mmio, DST_PITCH, dst_pitch ); + radeon_out32( mmio, DST_OFFSET, + adev->RADEON_display_base_addr + dst_offset_v ); + radeon_out32( mmio, SRC_PITCH, src_pitch ); + radeon_out32( mmio, SRC_OFFSET, + adev->RADEON_display_base_addr + src_offset_v ); + radeon_out32( mmio, SC_TOP_LEFT, (clip.y1 << 16) | (clip.x1) ); + radeon_out32( mmio, SC_BOTTOM_RIGHT, + ((clip.y2 + 1) << 16) | (clip.x2 + 1) ); + + radeonDoBlit( adrv, adev, rect->x, rect->y, rect->w, rect->h, dx, dy ); + + /* restore registers */ + radeon_waitfifo( adrv, adev, 6 ); + radeon_out32( mmio, DST_PITCH, dst_buffer->video.pitch ); + radeon_out32( mmio, DST_OFFSET, + adev->RADEON_display_base_addr + dst_buffer->video.offset ); + radeon_out32( mmio, SRC_PITCH, src_buffer->video.pitch ); + radeon_out32( mmio, SRC_OFFSET, + adev->RADEON_display_base_addr + src_buffer->video.offset ); + radeon_out32( mmio, SC_TOP_LEFT, (adev->clip.y1 << 16) | (adev->clip.x1) ); + radeon_out32( mmio, SC_BOTTOM_RIGHT, + ((adev->clip.y2 + 1) << 16) | (adev->clip.x2 + 1) ); + + return true; +} static DFBResult radeonWaitVSync( DisplayLayer *layer, @@ -393,6 +512,9 @@ driver_init_driver( GraphicsDevice #endif dfb_layers_hook_primary( device, driver_data, &radeonPrimaryFuncs, NULL, NULL ); + /* overlay support */ + dfb_layers_register( device, driver_data, &radeonOverlayFuncs ); + return DFB_OK; } @@ -435,6 +557,10 @@ driver_init_device( GraphicsDevice * GMC_DST_CLR_CMP_FCN_CLEAR | GMC_WRITE_MASK_DIS ); + /* get display base address */ + adev->RADEON_display_base_addr = radeon_in32( adrv->mmio_base, + DISPLAY_BASE_ADDR ); + return DFB_OK; } diff -urpN -X dontdiff DirectFB-0.9.20-clean/gfxdrivers/radeon/radeon.h DirectFB-0.9.20/gfxdrivers/radeon/radeon.h --- DirectFB-0.9.20-clean/gfxdrivers/radeon/radeon.h 2003-07-12 10:34:09.000000000 -0700 +++ DirectFB-0.9.20/gfxdrivers/radeon/radeon.h 2004-05-27 03:28:02.960982352 -0700 @@ -37,6 +37,7 @@ typedef struct { } RADEONDriverData; typedef struct { + DFBRegion clip; CoreSurface *source; CoreSurface *destination; DFBSurfaceBlittingFlags blittingflags; @@ -44,6 +45,7 @@ typedef struct { /* store some Radeon register values in native format */ __u32 RADEON_dp_gui_master_cntl; __u32 RADEON_color_compare; + __u32 RADEON_display_base_addr; /* state validation */ int v_destination; @@ -62,4 +64,6 @@ typedef struct { unsigned int fifo_cache_hits; } RADEONDeviceData; +extern DisplayLayerFuncs radeonOverlayFuncs; + #endif diff -urpN -X dontdiff DirectFB-0.9.20-clean/gfxdrivers/radeon/radeon_overlay.c DirectFB-0.9.20/gfxdrivers/radeon/radeon_overlay.c --- DirectFB-0.9.20-clean/gfxdrivers/radeon/radeon_overlay.c 1969-12-31 16:00:00.000000000 -0800 +++ DirectFB-0.9.20/gfxdrivers/radeon/radeon_overlay.c 2004-04-12 12:05:12.000000000 -0700 @@ -0,0 +1,633 @@ +/* + (c) Copyright 2000-2002 convergence integrated media GmbH. + (c) Copyright 2002 convergence GmbH. + + All rights reserved. + + Written by Alex Song + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include +#include +#include + +#include "radeon_regs.h" +#include "radeon_mmio.h" +#include "radeon.h" + +typedef struct { + DFBRectangle dest; + DFBDisplayLayerConfig config; + + /* overlay registers */ + struct { + __u32 H_INC; + __u32 STEP_BY; + __u32 Y_X_START; + __u32 Y_X_END; + __u32 V_INC; + __u32 P1_BLANK_LINES_AT_TOP; + __u32 P23_BLANK_LINES_AT_TOP; + __u32 VID_BUF_PITCH0_VALUE; + __u32 VID_BUF_PITCH1_VALUE; + __u32 P1_X_START_END; + __u32 P2_X_START_END; + __u32 P3_X_START_END; + __u32 VID_BUF0_BASE_ADRS; + __u32 VID_BUF1_BASE_ADRS; + __u32 VID_BUF2_BASE_ADRS; + __u32 P1_V_ACCUM_INIT; + __u32 P23_V_ACCUM_INIT; + __u32 P1_H_ACCUM_INIT; + __u32 P23_H_ACCUM_INIT; + __u32 KEY_CNTL; + __u32 DISP_MERGE; + __u32 SCALE_CNTL; + } regs; +} RADEONOverlayData; + +static void +radeon_ov0_waitidle(RADEONDriverData *rdrv); + +static void +radeon_ov0_waitfifo(RADEONDriverData *rdrv, unsigned int requested_fifo_space); + +static void +radeon_ov0_set_regs(RADEONDriverData *rdrv, RADEONOverlayData *rov0); + +static void +radeon_ov0_calc_regs(RADEONDriverData *rdrv, RADEONOverlayData *rov0, + DisplayLayer *layer, DFBDisplayLayerConfig *config); + +/**********************/ + +static int +radeon_ov0_LayerDataSize() +{ + return sizeof(RADEONOverlayData); +} + +static DFBResult +radeon_ov0_InitLayer(GraphicsDevice *device, + DisplayLayer *layer, + DisplayLayerInfo *layer_info, + DFBDisplayLayerConfig *default_config, + DFBColorAdjustment *default_adj, + void *driver_data, + void *layer_data) +{ + RADEONDriverData *rdrv = (RADEONDriverData*) driver_data; + RADEONOverlayData *rov0 = (RADEONOverlayData*) layer_data; + volatile __u8 *mmio = rdrv->mmio_base; + + /* set capabilities and type */ + layer_info->desc.caps = (DLCAPS_SCREEN_LOCATION | DLCAPS_SURFACE | + DLCAPS_SRC_COLORKEY | DLCAPS_DST_COLORKEY | + DLCAPS_OPACITY | DLCAPS_ALPHACHANNEL); + layer_info->desc.type = DLTF_VIDEO | DLTF_STILL_PICTURE; + + /* set name */ + snprintf(layer_info->desc.name, + DFB_DISPLAY_LAYER_DESC_NAME_LENGTH, "Radeon Overlay"); + + /* fill out the default configuration */ + default_config->flags = (DLCONF_WIDTH | DLCONF_HEIGHT | + DLCONF_PIXELFORMAT | DLCONF_BUFFERMODE | + DLCONF_OPTIONS); + default_config->width = 640; + default_config->height = 480; + default_config->pixelformat = DSPF_YUY2; + default_config->buffermode = DLBM_FRONTONLY; + default_config->options = DLOP_NONE; + + /* fill out default color adjustment, + only fields set in flags will be accepted from applications */ + default_adj->flags = DCAF_NONE; + + /* initialize destination rectangle */ + dfb_primary_layer_rectangle(0.0f, 0.0f, 1.0f, 1.0f, &rov0->dest); + + /* reset overlay */ + radeon_ov0_waitidle(rdrv); + radeon_out32(mmio, OV0_SCALE_CNTL, 0x80000000); + radeon_out32(mmio, OV0_AUTO_FLIP_CNTL, 0); + radeon_out32(mmio, OV0_EXCLUSIVE_HORZ, 0); + radeon_out32(mmio, OV0_FILTER_CNTL, 0x0000000f); + radeon_out32(mmio, OV0_KEY_CNTL, 0); + radeon_out32(mmio, OV0_TEST, 0); + + /* make overlay visible */ + rov0->regs.DISP_MERGE = (DISP_OV0_ALPHA_MASK | DISP_GRPH_ALPHA_MASK | + DISP_ALPHA_MODE_GLOBAL); + radeon_out32(mmio, DISP_MERGE_CNTL, rov0->regs.DISP_MERGE); + + return DFB_OK; +} + +static void +radeon_ov0_OnOff(RADEONDriverData *rdrv, + RADEONOverlayData *rov0, + int on) +{ + /* set/clear enable bit */ + if (on) + rov0->regs.SCALE_CNTL |= SCALER_ENABLE; + else + rov0->regs.SCALE_CNTL &= ~SCALER_ENABLE; + + /* write back to card */ + radeon_out32(rdrv->mmio_base, OV0_SCALE_CNTL, rov0->regs.SCALE_CNTL); +} + +static DFBResult +radeon_ov0_Enable(DisplayLayer *layer, + void *driver_data, + void *layer_data) +{ + RADEONDriverData *rdrv = (RADEONDriverData*) driver_data; + RADEONOverlayData *rov0 = (RADEONOverlayData*) layer_data; + + /* enable overlay */ + radeon_ov0_OnOff(rdrv, rov0, 1); + + return DFB_OK; +} + +static DFBResult +radeon_ov0_Disable(DisplayLayer *layer, + void *driver_data, + void *layer_data) +{ + RADEONDriverData *rdrv = (RADEONDriverData*) driver_data; + RADEONOverlayData *rov0 = (RADEONOverlayData*) layer_data; + + /* disable overlay */ + radeon_ov0_OnOff(rdrv, rov0, 0); + + return DFB_OK; +} + +static DFBResult +radeon_ov0_TestConfiguration(DisplayLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerConfig *config, + DFBDisplayLayerConfigFlags *failed) +{ + DFBDisplayLayerConfigFlags fail = 0; + + /* check for unsupported options */ + /* radeon overlay only supports one option at a time */ + switch (config->options) { + case DLOP_NONE: + case DLOP_SRC_COLORKEY: + break; + case DLOP_ALPHACHANNEL: + switch (dfb_primary_layer_pixelformat()) { + case DSPF_ARGB1555: + case DSPF_ARGB: + break; + default: + fail |= DLCONF_OPTIONS; + break; + } + break; + case DLOP_DST_COLORKEY: + case DLOP_OPACITY: + break; + default: + fail |= DLCONF_OPTIONS; + break; + } + + /* check pixel format */ + switch (config->pixelformat) { + case DSPF_ARGB: + case DSPF_YUY2: + case DSPF_UYVY: + case DSPF_I420: + case DSPF_YV12: + break; + default: + fail |= DLCONF_PIXELFORMAT; + break; + } + + /* check width */ + if (config->width > 2048 || config->width < 1) + fail |= DLCONF_WIDTH; + + /* check height */ + if (config->height > 2048 || config->height < 1) + fail |= DLCONF_HEIGHT; + + /* write back failing fields */ + if (failed) + *failed = fail; + + /* return failure if any field failed */ + if (fail) + return DFB_UNSUPPORTED; + + return DFB_OK; +} + +static DFBResult +radeon_ov0_SetConfiguration(DisplayLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerConfig *config) +{ + RADEONDriverData *rdrv = (RADEONDriverData*) driver_data; + RADEONOverlayData *rov0 = (RADEONOverlayData*) layer_data; + + /* remember configuration */ + rov0->config = *config; + + radeon_ov0_calc_regs(rdrv, rov0, layer, config); + radeon_ov0_set_regs(rdrv, rov0); + + return DFB_OK; +} + +static DFBResult +radeon_ov0_SetOpacity(DisplayLayer *layer, + void *driver_data, + void *layer_data, + __u8 opacity) +{ + RADEONDriverData *rdrv = (RADEONDriverData*) driver_data; + RADEONOverlayData *rov0 = (RADEONOverlayData*) layer_data; + volatile __u8 *mmio = rdrv->mmio_base; + + if ((rov0->config.options &DLOP_OPACITY) == 0) + return DFB_UNSUPPORTED; + + rov0->regs.DISP_MERGE &= ~DISP_OV0_ALPHA_MASK; + rov0->regs.DISP_MERGE |= (opacity << 24); + + radeon_out32(mmio, DISP_MERGE_CNTL, rov0->regs.DISP_MERGE); + + return DFB_OK; +} + +static DFBResult +radeon_ov0_SetScreenLocation(DisplayLayer *layer, + void *driver_data, + void *layer_data, + float x, + float y, + float width, + float height) +{ + RADEONDriverData *rdrv = (RADEONDriverData*) driver_data; + RADEONOverlayData *rov0 = (RADEONOverlayData*) layer_data; + + /* get new destination rectangle */ + dfb_primary_layer_rectangle(x, y, width, height, &rov0->dest); + + radeon_ov0_calc_regs(rdrv, rov0, layer, &rov0->config); + radeon_ov0_set_regs(rdrv, rov0); + + return DFB_OK; +} + +static DFBResult +radeon_ov0_SetSrcColorKey(DisplayLayer *layer, + void *driver_data, + void *layer_data, + __u8 r, + __u8 g, + __u8 b) +{ + return DFB_UNIMPLEMENTED; +} + +static DFBResult +radeon_ov0_SetDstColorKey(DisplayLayer *layer, + void *driver_data, + void *layer_data, + __u8 r, + __u8 g, + __u8 b) +{ + RADEONDriverData *rdrv = (RADEONDriverData*) driver_data; + RADEONOverlayData *rov0 = (RADEONOverlayData*) layer_data; + volatile __u8 *mmio = rdrv->mmio_base; + __u32 key; + + if ((rov0->config.options & DLOP_DST_COLORKEY) == 0) + return DFB_UNSUPPORTED; + + switch (dfb_primary_layer_pixelformat()) { + case DSPF_RGB332: + r = (r & 0xE0) | ((g & 0xE0) >> 3) | ((b & 0xC0) >> 6); + g = r; + b = r; + break; + case DSPF_ARGB1555: + r &= 0xF8; + g &= 0xF8; + b &= 0xF8; + break; + case DSPF_RGB16: + r &= 0xF8; + g &= 0xFC; + b &= 0xF8; + break; + case DSPF_RGB32: + case DSPF_ARGB: + break; + default: + return DFB_UNSUPPORTED; + } + + key = (r << 16) | (g << 8) | (b); + + radeon_ov0_waitfifo(rdrv, 2); + radeon_out32(mmio, OV0_GRAPHICS_KEY_CLR_HIGH, (0xff << 24) | key); + radeon_out32(mmio, OV0_GRAPHICS_KEY_CLR_LOW, key); + + return DFB_OK; +} + +static DFBResult +radeon_ov0_FlipBuffers(DisplayLayer *layer, + void *driver_data, + void *layer_data, + DFBSurfaceFlipFlags flags) +{ + RADEONDriverData *rdrv = (RADEONDriverData*) driver_data; + RADEONOverlayData *rov0 = (RADEONOverlayData*) layer_data; + CoreSurface *surface = dfb_layer_surface(layer); + + dfb_surface_flip_buffers(surface); + + radeon_ov0_calc_regs(rdrv, rov0, layer, &rov0->config); + radeon_ov0_set_regs(rdrv, rov0); + + if ((flags & DSFLIP_WAIT) != 0) + dfb_layer_wait_vsync(layer); + + return DFB_OK; +} + +static DFBResult +radeon_ov0_SetColorAdjustment(DisplayLayer *layer, + void *driver_data, + void *layer_data, + DFBColorAdjustment *adj) +{ + return DFB_UNIMPLEMENTED; +} + +static DFBResult +radeon_ov0_WaitVSync(DisplayLayer *layer, + void *driver_data, + void *layer_data) +{ + return dfb_layer_wait_vsync(dfb_layer_at(DLID_PRIMARY)); +} + +DisplayLayerFuncs radeonOverlayFuncs = { + LayerDataSize: radeon_ov0_LayerDataSize, + InitLayer: radeon_ov0_InitLayer, + Enable: radeon_ov0_Enable, + Disable: radeon_ov0_Disable, + TestConfiguration: radeon_ov0_TestConfiguration, + SetConfiguration: radeon_ov0_SetConfiguration, + SetOpacity: radeon_ov0_SetOpacity, + SetScreenLocation: radeon_ov0_SetScreenLocation, + SetSrcColorKey: radeon_ov0_SetSrcColorKey, + SetDstColorKey: radeon_ov0_SetDstColorKey, + FlipBuffers: radeon_ov0_FlipBuffers, + SetColorAdjustment: radeon_ov0_SetColorAdjustment, + WaitVSync: radeon_ov0_WaitVSync +}; + + +/* internal */ + +static void +radeon_ov0_waitidle(RADEONDriverData *rdrv) +{ + volatile __u8 *mmio = rdrv->mmio_base; + int timeout = 1000000; + + while (timeout--) { + if ((radeon_in32(mmio, RBBM_STATUS) & RBBM_FIFOCNT_MASK) == 64) + break; + } + + timeout = 1000000; + + while (timeout--) { + if ((radeon_in32(mmio, RBBM_STATUS) & RBBM_ACTIVE) == ENGINE_IDLE) + break; + } +} + +static void +radeon_ov0_waitfifo(RADEONDriverData *rdrv, unsigned int requested_fifo_space) +{ + volatile __u8 *mmio = rdrv->mmio_base; + int timeout = 1000000; + unsigned int fifo_space; + + while (timeout--) { + fifo_space = radeon_in32(mmio, RBBM_STATUS) & RBBM_FIFOCNT_MASK; + if (fifo_space >= requested_fifo_space) + break; + } +} + +static void +radeon_ov0_set_regs(RADEONDriverData *rdrv, RADEONOverlayData *rov0) +{ + volatile __u8 *mmio = rdrv->mmio_base; + + radeon_ov0_waitfifo(rdrv, 2); + radeon_out32(mmio, OV0_REG_LOAD_CNTL, 1); + radeon_ov0_waitidle(rdrv); + while (!(radeon_in32(mmio, OV0_REG_LOAD_CNTL) & (1 << 3))); + + radeon_ov0_waitfifo(rdrv, 15); + radeon_out32(mmio, OV0_H_INC, rov0->regs.H_INC); + radeon_out32(mmio, OV0_STEP_BY, rov0->regs.STEP_BY); + radeon_out32(mmio, OV0_Y_X_START, rov0->regs.Y_X_START); + radeon_out32(mmio, OV0_Y_X_END, rov0->regs.Y_X_END); + radeon_out32(mmio, OV0_V_INC, rov0->regs.V_INC); + radeon_out32(mmio, OV0_P1_BLANK_LINES_AT_TOP, + rov0->regs.P1_BLANK_LINES_AT_TOP); + radeon_out32(mmio, OV0_P23_BLANK_LINES_AT_TOP, + rov0->regs.P23_BLANK_LINES_AT_TOP); + radeon_out32(mmio, OV0_VID_BUF_PITCH0_VALUE, + rov0->regs.VID_BUF_PITCH0_VALUE); + radeon_out32(mmio, OV0_VID_BUF_PITCH1_VALUE, + rov0->regs.VID_BUF_PITCH1_VALUE); + radeon_out32(mmio, OV0_P1_X_START_END, rov0->regs.P1_X_START_END); + radeon_out32(mmio, OV0_P2_X_START_END, rov0->regs.P2_X_START_END); + radeon_out32(mmio, OV0_P3_X_START_END, rov0->regs.P3_X_START_END); + radeon_out32(mmio, OV0_VID_BUF0_BASE_ADRS, rov0->regs.VID_BUF0_BASE_ADRS); + radeon_out32(mmio, OV0_VID_BUF1_BASE_ADRS, rov0->regs.VID_BUF1_BASE_ADRS); + radeon_out32(mmio, OV0_VID_BUF2_BASE_ADRS, rov0->regs.VID_BUF2_BASE_ADRS); + + radeon_ov0_waitfifo(rdrv, 8); + radeon_out32(mmio, OV0_P1_V_ACCUM_INIT, rov0->regs.P1_V_ACCUM_INIT); + radeon_out32(mmio, OV0_P23_V_ACCUM_INIT, rov0->regs.P23_V_ACCUM_INIT); + radeon_out32(mmio, OV0_P1_H_ACCUM_INIT, rov0->regs.P1_H_ACCUM_INIT); + radeon_out32(mmio, OV0_P23_H_ACCUM_INIT, rov0->regs.P23_H_ACCUM_INIT); + radeon_out32(mmio, OV0_KEY_CNTL, rov0->regs.KEY_CNTL); + radeon_out32(mmio, DISP_MERGE_CNTL, rov0->regs.DISP_MERGE); + radeon_out32(mmio, OV0_SCALE_CNTL, rov0->regs.SCALE_CNTL); + + radeon_out32(mmio, OV0_REG_LOAD_CNTL, 0); +} + +static void +radeon_ov0_calc_regs(RADEONDriverData *rdrv, RADEONOverlayData *rov0, + DisplayLayer *layer, DFBDisplayLayerConfig *config) +{ + int h_inc, v_inc, step_by, tmp; + int p1_h_accum_init, p23_h_accum_init; + int p1_v_accum_init, p23_v_accum_init; + + DFBRegion dstBox; + int dst_w; + int dst_h; + __u32 offset_u = 0, offset_v = 0; + + CoreSurface *surface = dfb_layer_surface(layer); + SurfaceBuffer *front_buffer = surface->front_buffer; + + /* destination box */ + dstBox.x1 = rov0->dest.x; + dstBox.y1 = rov0->dest.y; + dstBox.x2 = rov0->dest.x + rov0->dest.w; + dstBox.y2 = rov0->dest.y + rov0->dest.h; + + /* destination size */ + dst_w = rov0->dest.w; + dst_h = rov0->dest.h; + + /* calculate incrementors */ + h_inc = (surface->width << 12) / dst_w; + v_inc = (surface->height << 20) / dst_h; + step_by = 1; + + while (h_inc >= (2 << 12)) { + step_by++; + h_inc >>= 1; + } + + /* calculate values for horizontal accumulators */ + tmp = 0x00028000 + (h_inc << 3); + p1_h_accum_init = ((tmp << 4) & 0x000f8000) | ((tmp << 12) & 0xf0000000); + + tmp = 0x00028000 + (h_inc << 2); + p23_h_accum_init = ((tmp << 4) & 0x000f8000) | ((tmp << 12) & 0x70000000); + + /* calculate values for vertical accumulators */ + tmp = 0x00018000; + p1_v_accum_init = ((tmp << 4) & 0x03ff8000) | 0x00000001; + + tmp = 0x00018000; + p23_v_accum_init = ((tmp << 4) & 0x01ff8000) | 0x00000001; + + /* clear everything but the enable bit that may be set*/ + rov0->regs.SCALE_CNTL &= SCALER_ENABLE; + + /* choose pixel format and calculate buffer offsets for planar modes */ + switch (surface->format) { + case DSPF_ARGB: + rov0->regs.SCALE_CNTL |= SCALER_SOURCE_32BPP; + break; + case DSPF_UYVY: + rov0->regs.SCALE_CNTL |= SCALER_SOURCE_YVYU422; + break; + case DSPF_YUY2: + rov0->regs.SCALE_CNTL |= SCALER_SOURCE_VYUY422; + break; + case DSPF_I420: + rov0->regs.SCALE_CNTL |= SCALER_SOURCE_YUV12; + offset_u = front_buffer->video.offset + + surface->height * front_buffer->video.pitch; + offset_v = offset_u + + (surface->height >> 1) * (front_buffer->video.pitch >> 1); + break; + case DSPF_YV12: + rov0->regs.SCALE_CNTL |= SCALER_SOURCE_YUV12; + offset_v = front_buffer->video.offset + + surface->height * front_buffer->video.pitch; + offset_u = offset_v + + (surface->height >> 1) * (front_buffer->video.pitch >> 1); + break; + default: + BUG("unexpected pixelformat"); + rov0->regs.SCALE_CNTL = 0; + return; + } + + /* layer options */ + switch (config->options) { + case DLOP_ALPHACHANNEL: + rov0->regs.KEY_CNTL = 0; + rov0->regs.DISP_MERGE &= ~DISP_ALPHA_MODE_MASK; + rov0->regs.DISP_MERGE |= DISP_ALPHA_MODE_PER_PIXEL; + break; + case DLOP_DST_COLORKEY: + rov0->regs.KEY_CNTL = CMP_MIX_OR | GRAPHIC_KEY_FN_EQ | VIDEO_KEY_FN_FALSE; + rov0->regs.DISP_MERGE &= ~DISP_ALPHA_MODE_MASK; + rov0->regs.DISP_MERGE |= DISP_ALPHA_MODE_KEY; + break; + case DLOP_OPACITY: + /* fall through */ + default: + rov0->regs.KEY_CNTL = 0; + rov0->regs.DISP_MERGE &= ~DISP_ALPHA_MODE_MASK; + rov0->regs.DISP_MERGE |= DISP_ALPHA_MODE_GLOBAL; + break; + } + + rov0->regs.SCALE_CNTL |= SCALER_DOUBLE_BUFFER | + SCALER_ADAPTIVE_DEINT | + SCALER_SMART_SWITCH | + SCALER_BURST_PER_PLANE; + + rov0->regs.H_INC = h_inc | ((h_inc >> 1) << 16); + rov0->regs.V_INC = v_inc; + rov0->regs.STEP_BY = step_by | (step_by << 8); + rov0->regs.Y_X_START = dstBox.x1 | (dstBox.y1 << 16); + rov0->regs.Y_X_END = dstBox.x2 | (dstBox.y2 << 16); + rov0->regs.P1_BLANK_LINES_AT_TOP = 0x00000fff | ((surface->height - 1) << 16); + rov0->regs.P23_BLANK_LINES_AT_TOP = 0x000007ff | ((((surface->height + 1) >> 1) - 1) << 16); + rov0->regs.VID_BUF_PITCH0_VALUE = front_buffer->video.pitch; + rov0->regs.VID_BUF_PITCH1_VALUE = front_buffer->video.pitch >> 1; + rov0->regs.P1_X_START_END = surface->width - 1; + rov0->regs.P2_X_START_END = (surface->width >> 1) - 1; + rov0->regs.P3_X_START_END = (surface->width >> 1) - 1; + + rov0->regs.VID_BUF0_BASE_ADRS = front_buffer->video.offset & 0x07fffff0; + rov0->regs.VID_BUF1_BASE_ADRS = (offset_u & 0x07fffff0) | 1; + rov0->regs.VID_BUF2_BASE_ADRS = (offset_v & 0x07fffff0) | 1; + + rov0->regs.P1_H_ACCUM_INIT = p1_h_accum_init; + rov0->regs.P23_H_ACCUM_INIT = p23_h_accum_init; + rov0->regs.P1_V_ACCUM_INIT = p1_v_accum_init; + rov0->regs.P23_V_ACCUM_INIT = p23_v_accum_init; +} diff -urpN -X dontdiff DirectFB-0.9.20-clean/gfxdrivers/radeon/radeon_regs.h DirectFB-0.9.20/gfxdrivers/radeon/radeon_regs.h --- DirectFB-0.9.20-clean/gfxdrivers/radeon/radeon_regs.h 2003-07-13 15:26:17.000000000 -0700 +++ DirectFB-0.9.20/gfxdrivers/radeon/radeon_regs.h 2004-05-27 03:33:46.928691312 -0700 @@ -33,6 +33,18 @@ #define CRTC_VBLANK_SAVE 0x00000002 #define CRTC_VBLANK_SAVE_CLEAR 0x00000002 +#define DISPLAY_BASE_ADDR 0x023c + +#define DISP_MERGE_CNTL 0x0d60 +# define DISP_ALPHA_MODE_MASK 0x03 +# define DISP_ALPHA_MODE_KEY 0 +# define DISP_ALPHA_MODE_PER_PIXEL 1 +# define DISP_ALPHA_MODE_GLOBAL 2 +# define DISP_RGB_OFFSET_EN (1<<8) +# define DISP_GRPH_ALPHA_MASK (0xff << 16) +# define DISP_OV0_ALPHA_MASK (0xff << 24) +# define DISP_LIN_TRANS_BYPASS (0x01 << 9) + #define RBBM_STATUS 0x0e40 #define RBBM_FIFOCNT_MASK 0x0000007f #define RBBM_ACTIVE 0x80000000 @@ -116,8 +128,147 @@ #define SC_BOTTOM_RIGHT 0x16f0 #define SRC_SC_BOTTOM_RIGHT 0x16f4 - /* CONSTANTS */ #define ENGINE_IDLE 0x0 + +/* radeon overlay registers */ +#define OV0_AUTO_FLIP_CNTL 0x0470 +#define OV0_COLOUR_CNTL 0x04E0 +#define OV0_DEINTERLACE_PATTERN 0x0474 +#define OV0_EXCLUSIVE_HORZ 0x0408 +# define EXCL_HORZ_START_MASK 0x000000ff +# define EXCL_HORZ_END_MASK 0x0000ff00 +# define EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 +# define EXCL_HORZ_EXCLUSIVE_EN 0x80000000 +#define OV0_EXCLUSIVE_VERT 0x040C +# define EXCL_VERT_START_MASK 0x000003ff +# define EXCL_VERT_END_MASK 0x03ff0000 +#define OV0_FILTER_CNTL 0x04A0 +#define OV0_FOUR_TAP_COEF_0 0x04B0 +#define OV0_FOUR_TAP_COEF_1 0x04B4 +#define OV0_FOUR_TAP_COEF_2 0x04B8 +#define OV0_FOUR_TAP_COEF_3 0x04BC +#define OV0_FOUR_TAP_COEF_4 0x04C0 +#define OV0_GAMMA_000_00F 0x0d40 +#define OV0_GAMMA_010_01F 0x0d44 +#define OV0_GAMMA_020_03F 0x0d48 +#define OV0_GAMMA_040_07F 0x0d4c +#define OV0_GAMMA_080_0BF 0x0e00 +#define OV0_GAMMA_0C0_0FF 0x0e04 +#define OV0_GAMMA_100_13F 0x0e08 +#define OV0_GAMMA_140_17F 0x0e0c +#define OV0_GAMMA_180_1BF 0x0e10 +#define OV0_GAMMA_1C0_1FF 0x0e14 +#define OV0_GAMMA_200_23F 0x0e18 +#define OV0_GAMMA_240_27F 0x0e1c +#define OV0_GAMMA_280_2BF 0x0e20 +#define OV0_GAMMA_2C0_2FF 0x0e24 +#define OV0_GAMMA_300_33F 0x0e28 +#define OV0_GAMMA_340_37F 0x0e2c +#define OV0_GAMMA_380_3BF 0x0d50 +#define OV0_GAMMA_3C0_3FF 0x0d54 +#define OV0_GRAPHICS_KEY_CLR_LOW 0x04EC +#define OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0 +#define OV0_H_INC 0x0480 +#define OV0_KEY_CNTL 0x04F4 +# define VIDEO_KEY_FN_MASK 0x00000003L +# define VIDEO_KEY_FN_FALSE 0x00000000L +# define VIDEO_KEY_FN_TRUE 0x00000001L +# define VIDEO_KEY_FN_EQ 0x00000002L +# define VIDEO_KEY_FN_NE 0x00000003L +# define GRAPHIC_KEY_FN_MASK 0x00000030L +# define GRAPHIC_KEY_FN_FALSE 0x00000000L +# define GRAPHIC_KEY_FN_TRUE 0x00000010L +# define GRAPHIC_KEY_FN_EQ 0x00000020L +# define GRAPHIC_KEY_FN_NE 0x00000030L +# define CMP_MIX_MASK 0x00000100L +# define CMP_MIX_OR 0x00000000L +# define CMP_MIX_AND 0x00000100L +#define OV0_LIN_TRANS_A 0x0d20 +#define OV0_LIN_TRANS_B 0x0d24 +#define OV0_LIN_TRANS_C 0x0d28 +#define OV0_LIN_TRANS_D 0x0d2c +#define OV0_LIN_TRANS_E 0x0d30 +#define OV0_LIN_TRANS_F 0x0d34 +#define OV0_P1_BLANK_LINES_AT_TOP 0x0430 +# define P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL +# define P1_ACTIVE_LINES_M1 0x0fff0000L +#define OV0_P1_H_ACCUM_INIT 0x0488 +#define OV0_P1_V_ACCUM_INIT 0x0428 +# define OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L +# define OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L +#define OV0_P1_X_START_END 0x0494 +#define OV0_P2_X_START_END 0x0498 +#define OV0_P23_BLANK_LINES_AT_TOP 0x0434 +# define P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL +# define P23_ACTIVE_LINES_M1 0x07ff0000L +#define OV0_P23_H_ACCUM_INIT 0x048C +#define OV0_P23_V_ACCUM_INIT 0x042C +#define OV0_P3_X_START_END 0x049C +#define OV0_REG_LOAD_CNTL 0x0410 +# define REG_LD_CTL_LOCK 0x00000001L +# define REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L +# define REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L +# define REG_LD_CTL_LOCK_READBACK 0x00000008L +#define OV0_SCALE_CNTL 0x0420 +# define SCALER_HORZ_PICK_NEAREST 0x00000004L +# define SCALER_VERT_PICK_NEAREST 0x00000008L +# define SCALER_SIGNED_UV 0x00000010L +# define SCALER_GAMMA_SEL_MASK 0x00000060L +# define SCALER_GAMMA_SEL_BRIGHT 0x00000000L +# define SCALER_GAMMA_SEL_G22 0x00000020L +# define SCALER_GAMMA_SEL_G18 0x00000040L +# define SCALER_GAMMA_SEL_G14 0x00000060L +# define SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L +# define SCALER_SURFAC_FORMAT 0x00000f00L +# define SCALER_SOURCE_15BPP 0x00000300L +# define SCALER_SOURCE_16BPP 0x00000400L +# define SCALER_SOURCE_32BPP 0x00000600L +# define SCALER_SOURCE_YUV9 0x00000900L +# define SCALER_SOURCE_YUV12 0x00000A00L +# define SCALER_SOURCE_VYUY422 0x00000B00L +# define SCALER_SOURCE_YVYU422 0x00000C00L +# define SCALER_ADAPTIVE_DEINT 0x00001000L +# define SCALER_TEMPORAL_DEINT 0x00002000L +# define SCALER_SMART_SWITCH 0x00008000L +# define SCALER_BURST_PER_PLANE 0x007F0000L +# define SCALER_DOUBLE_BUFFER 0x01000000L +# define SCALER_DIS_LIMIT 0x08000000L +# define SCALER_INT_EMU 0x20000000L +# define SCALER_ENABLE 0x40000000L +# define SCALER_SOFT_RESET 0x80000000L +#define OV0_STEP_BY 0x0484 +#define OV0_TEST 0x04F8 +#define OV0_V_INC 0x0424 +#define OV0_VID_BUF_PITCH0_VALUE 0x0460 +#define OV0_VID_BUF_PITCH1_VALUE 0x0464 +#define OV0_VID_BUF0_BASE_ADRS 0x0440 +# define VIF_BUF0_PITCH_SEL 0x00000001L +# define VIF_BUF0_TILE_ADRS 0x00000002L +# define VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF1_BASE_ADRS 0x0444 +# define VIF_BUF1_PITCH_SEL 0x00000001L +# define VIF_BUF1_TILE_ADRS 0x00000002L +# define VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF2_BASE_ADRS 0x0448 +# define VIF_BUF2_PITCH_SEL 0x00000001L +# define VIF_BUF2_TILE_ADRS 0x00000002L +# define VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF3_BASE_ADRS 0x044C +#define OV0_VID_BUF4_BASE_ADRS 0x0450 +#define OV0_VID_BUF5_BASE_ADRS 0x0454 +#define OV0_VIDEO_KEY_CLR_HIGH 0x04E8 +#define OV0_VIDEO_KEY_CLR_LOW 0x04E4 +#define OV0_Y_X_START 0x0400 +#define OV0_Y_X_END 0x0404 +#define OV1_Y_X_START 0x0600 +#define OV1_Y_X_END 0x0604 +#define OVR_CLR 0x0230 +#define OVR_WID_LEFT_RIGHT 0x0234 +#define OVR_WID_TOP_BOTTOM 0x0238 + #endif diff -urpN -X dontdiff DirectFB-0.9.20-clean/gfxdrivers/radeon/radeon_state.c DirectFB-0.9.20/gfxdrivers/radeon/radeon_state.c --- DirectFB-0.9.20-clean/gfxdrivers/radeon/radeon_state.c 2003-07-12 10:34:09.000000000 -0700 +++ DirectFB-0.9.20/gfxdrivers/radeon/radeon_state.c 2004-05-27 03:34:30.485069736 -0700 @@ -51,6 +51,8 @@ void radeon_set_destination( RADEONDrive return; switch ( state->destination->format ) { + case DSPF_I420: + case DSPF_YV12: case DSPF_RGB332: adev->RADEON_dp_gui_master_cntl = GMC_DST_8BPP; break; @@ -80,6 +82,7 @@ void radeon_set_destination( RADEONDrive state->destination->back_buffer->video.pitch ); radeon_out32( adrv->mmio_base, DST_OFFSET, + adev->RADEON_display_base_addr + state->destination->back_buffer->video.offset ); adev->destination = state->destination; @@ -96,6 +99,8 @@ void radeon_set_source( RADEONDriverData radeon_waitfifo( adrv, adev, 3 ); switch ( state->source->format ) { + case DSPF_I420: + case DSPF_YV12: case DSPF_RGB332: radeon_out32( adrv->mmio_base, CLR_CMP_MASK, 0x000000FF ); break; @@ -118,6 +123,7 @@ void radeon_set_source( RADEONDriverData state->source->front_buffer->video.pitch ); radeon_out32( adrv->mmio_base, SRC_OFFSET, + adev->RADEON_display_base_addr + state->source->front_buffer->video.offset ); adev->source = state->source;