Hi,
When playing video using DirectFB and ATI Radeon 9600 card
the screen stays black. By comparing the radeon driver
with the VIDIX driver I found some registers that need
to be initialized. Also the chip type has to be known,
so I copied the probing function from the R200 driver.
The included patch contains all the necesary changes,
please applay.
BTW, all drivers contain similar probing functions that
determine the chipset type by searching PCI vendor id and
device id from sysfs or proc filesystem. Shouldn't a
function like this be in the core instead of every driver ?
Regards,
Vadim Catana
diff -urN ./DirectFB/gfxdrivers/radeon/radeon.c ./DirectFB.test/gfxdrivers/radeon/radeon.c
--- ./DirectFB/gfxdrivers/radeon/radeon.c 2004-11-22 20:09:43.000000000 +0200
+++ ./DirectFB.test/gfxdrivers/radeon/radeon.c 2005-07-05 08:50:32.000000000 +0300
@@ -36,6 +36,10 @@
#include <fcntl.h>
#include <sys/ioctl.h>
+#ifdef USE_SYSFS
+# include <sysfs/libsysfs.h>
+#endif
+
#include <linux/fb.h>
#include <directfb.h>
@@ -419,19 +423,115 @@
};
-/* exported symbols */
+/* probe functions */
-static int
-driver_probe( GraphicsDevice *device )
+static int
+radeon_probe_chipset( int *ret_index )
{
- switch ( dfb_gfxcard_get_accelerator( device ) ) {
- case FB_ACCEL_ATI_RADEON: /* ATI Radeon */
- return 1;
+ char buf[512];
+ __u32 chip = 0;
+ int found = -1;
+ int i;
+
+#ifdef USE_SYSFS
+ if (!sysfs_get_mnt_path( buf, 512 )) {
+ struct dlist *devices;
+ struct sysfs_device *dev;
+ struct sysfs_attribute *attr;
+ int bus;
+
+ devices = sysfs_open_bus_devices_list( "pci" );
+ if (devices) {
+ dlist_for_each_data( devices, dev, struct sysfs_device ) {
+ if (sscanf( dev->name, "0000:%02x:", &bus ) < 1 || bus < 1)
+ continue;
+
+ dev = sysfs_open_device( "pci", dev->name );
+ if (dev) {
+ attr = sysfs_get_device_attr( dev, "vendor" );
+ if (attr && !strncmp( attr->value, "0x1002", 6 )) {
+ attr = sysfs_get_device_attr( dev, "device" );
+ if (attr) {
+ sscanf( attr->value, "0x%04x", &chip );
+ for (i = 0; i < sizeof(dev_table)/sizeof(dev_table[0]); i++) {
+ if (dev_table[i].id == chip) {
+ found = i;
+ break;
+ }
+ }
+ }
+ }
+ sysfs_close_device( dev );
+
+ if (found != -1)
+ break;
+ }
+ }
+
+ sysfs_close_list( devices );
+ }
}
+#endif /* USE_SYSFS */
+
+ /* try /proc interface */
+ if (found == -1) {
+ FILE *fp;
+ __u32 device;
+ __u32 vendor;
+
+ fp = fopen( "/proc/bus/pci/devices", "r" );
+ if (!fp) {
+ D_PERROR( "DirectFB/RADEON: couldn't access /proc/bus/pci/devices!\n" );
+ return 0;
+ }
+ while (found == -1 && fgets( buf, 512, fp )) {
+ if (sscanf( buf, "%04x\t%04x%04x", &device, &vendor, &chip ) == 3)
+ {
+ if (device >= 0x0100 && vendor == 0x1002) {
+ for (i = 0; i < sizeof(dev_table)/sizeof(dev_table[0]); i++) {
+ if (dev_table[i].id == chip) {
+ found = i;
+ break;
+ }
+ }
+ }
+ }
+ }
+
+ fclose( fp );
+ }
+
+ if (found != -1) {
+ if (ret_index)
+ *ret_index = found;
+ return 1;
+ }
+
return 0;
}
+/* exported symbols */
+
+static int
+driver_probe( GraphicsDevice *device )
+{
+ return radeon_probe_chipset( NULL );
+}
+
+
+// static int
+// driver_probe( GraphicsDevice *device )
+// {
+// switch ( dfb_gfxcard_get_accelerator( device ) ) {
+// case FB_ACCEL_ATI_RADEON: /* ATI Radeon */
+// return 1;
+// }
+//
+// return 0;
+// }
+
+
static void
driver_get_info( GraphicsDevice *device,
GraphicsDriverInfo *info )
@@ -505,6 +605,17 @@
RADEONDeviceData *adev = ( RADEONDeviceData* ) device_data;
volatile __u8 *mmio = adrv->mmio_base;
+ int id = 0;
+
+ if (!radeon_probe_chipset( &id )) {
+ D_ERROR( "DirectFB/RADEON: no supported device found!\n" );
+ return DFB_FAILURE;
+ }
+
+ D_INFO( "DirectFB/RADEON: found %s\n", dev_table[id].name);
+
+ adev->chipset = dev_table[id].chip;
+
/* fill device info */
snprintf( device_info->name,
DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "Radeon" );
diff -urN ./DirectFB/gfxdrivers/radeon/radeon.h ./DirectFB.test/gfxdrivers/radeon/radeon.h
--- ./DirectFB/gfxdrivers/radeon/radeon.h 2004-04-29 17:57:56.000000000 +0300
+++ ./DirectFB.test/gfxdrivers/radeon/radeon.h 2005-07-05 08:35:25.000000000 +0300
@@ -33,11 +33,127 @@
#include <core/coretypes.h>
#include <core/layers.h>
+enum {
+ R_100,
+ R_120,
+ R_150,
+ R_200,
+ R_250,
+ R_280,
+ R_300,
+ R_350,
+ R_370,
+ R_380,
+ R_420
+};
+
+static struct {
+ __u16 id;
+ __u32 chip;
+ const char *name;
+} dev_table[] = {
+ { 0x5144, R_100, "Radeon R100 QD [Radeon 7200]" },
+ { 0x5145, R_100, "Radeon R100 QE" },
+ { 0x5146, R_100, "Radeon R100 QF" },
+ { 0x5147, R_100, "Radeon R100 QG" },
+ { 0x5159, R_120, "Radeon RV100 QY [Radeon 7000/VE]" },
+ { 0x515a, R_120, "Radeon RV100 QZ [Radeon 7000/VE]" },
+ { 0x4c59, R_120, "Radeon Mobility M6 LY" },
+ { 0x4c5a, R_120, "Radeon Mobility M6 LZ" },
+ { 0x4136, R_150, "Radeon IGP 320 M" },
+ { 0x4336, R_150, "Radeon Mobility U1" },
+ { 0x4c57, R_150, "Radeon Mobility M7 LW [Radeon Mobility 7500]" },
+ { 0x4c58, R_150, "Radeon RV200 LX [Mobility FireGL 7800 M7]" },
+ { 0x5157, R_150, "Radeon RV200 QW [Radeon 7500]" },
+ { 0x5158, R_150, "Radeon RV200 QX [Radeon 7500]" },
+ { 0x4242, R_200, "R200 BB [Radeon All in Wonder 8500DV]" },
+ { 0x4243, R_200, "R200 BC [Radeon All in Wonder 8500]" },
+ { 0x5148, R_200, "Radeon R200 QH [Radeon 8500]" },
+ { 0x5149, R_200, "Radeon R200 QI" },
+ { 0x514a, R_200, "Radeon R200 QJ" },
+ { 0x514b, R_200, "Radeon R200 QK" },
+ { 0x514c, R_200, "Radeon R200 QL [Radeon 8500 LE]" },
+ { 0x514d, R_200, "Radeon R200 QM [Radeon 9100]" },
+ { 0x514e, R_200, "Radeon R200 QN [Radeon 8500LE]" },
+ { 0x514f, R_200, "Radeon R200 QO [Radeon 8500LE]" },
+ { 0x5168, R_200, "Radeon R200 Qh" },
+ { 0x5169, R_200, "Radeon R200 Qi" },
+ { 0x516a, R_200, "Radeon R200 Qj" },
+ { 0x516b, R_200, "Radeon R200 Qk" },
+ { 0x516c, R_200, "Radeon R200 Ql" },
+ { 0x4137, R_200, "Radeon IGP330/340/350" },
+ { 0x4337, R_200, "Radeon IGP 330M/340M/350M" },
+ { 0x4967, R_250, "Radeon RV250 Ig [Radeon 9000]" },
+ { 0x4237, R_250, "Radeon 7000 IGP" },
+ { 0x4437, R_250, "Radeon Mobility 7000 IGP" },
+ { 0x4964, R_250, "Radeon RV250 Id [Radeon 9000]" },
+ { 0x4965, R_250, "Radeon RV250 Ie [Radeon 9000]" },
+ { 0x4966, R_250, "Radeon RV250 If [Radeon 9000]" },
+ { 0x4967, R_250, "Radeon RV250 Ig [Radeon 9000]" },
+ { 0x4c64, R_250, "Radeon R250 Ld [Radeon Mobility 9000 M9]" },
+ { 0x4c65, R_250, "Radeon R250 Le [Radeon Mobility 9000 M9]" },
+ { 0x4c66, R_250, "Radeon R250 Lf [FireGL 9000]" },
+ { 0x4c67, R_250, "Radeon R250 Lg [Radeon Mobility 9000 M9]" },
+ { 0x5960, R_280, "RV280 [Radeon 9200 PRO]" },
+ { 0x5961, R_280, "RV280 [Radeon 9200]" },
+ { 0x5962, R_280, "RV280 [Radeon 9200]" },
+ { 0x4147, R_300, "R300 AG [FireGL Z1/X1]" },
+ { 0x4e44, R_300, "Radeon R300 ND [Radeon 9700 Pro]" },
+ { 0x4e45, R_300, "Radeon R300 NE [Radeon 9500 Pro]" },
+ { 0x4e47, R_300, "Radeon R300 NG [FireGL X1]" },
+ { 0x4144, R_300, "R300 AD [Radeon 9500 Pro]" },
+ { 0x4145, R_300, "R300 AE [Radeon 9700 Pro]" },
+ { 0x4146, R_300, "R300 AF [Radeon 9700 Pro]" },
+ { 0x5834, R_300, "Radeon 9100 IGP" },
+ { 0x5835, R_300, "RS300M AGP [Radeon Mobility 9100IGP]" },
+ { 0x4e46, R_300, "RV350 NF [Radeon 9600]" },
+ { 0x4e4a, R_300, "RV350 NJ [Radeon 9800 XT]" },
+ { 0x4148, R_350, "R350 AH [Radeon 9800]" },
+ { 0x4149, R_350, "R350 AI [Radeon 9800]" },
+ { 0x414a, R_350, "R350 AJ [Radeon 9800]" },
+ { 0x414b, R_350, "R350 AK [Fire GL X2]" },
+ { 0x4e48, R_350, "Radeon R350 [Radeon 9800 Pro]" },
+ { 0x4e49, R_350, "Radeon R350 [Radeon 9800]" },
+ { 0x4e4a, R_350, "RV350 NJ [Radeon 9800 XT]" },
+ { 0x4e4b, R_350, "R350 NK [Fire GL X2]" },
+ { 0x4150, R_350, "RV350 AP [Radeon 9600]" },
+ { 0x4151, R_350, "RV350 AQ [Radeon 9600]" },
+ { 0x4152, R_350, "RV350 AR [Radeon 9600]" },
+ { 0x4153, R_350, "RV350 AS [Radeon 9600 AS]" },
+ { 0x4154, R_350, "RV350 AT [Fire GL T2]" },
+ { 0x4155, R_350, "RV350 AU [Fire GL T2]" },
+ { 0x4156, R_350, "RV350 AV [Fire GL T2]" },
+ { 0x4157, R_350, "RV350 AW [Fire GL T2]" },
+ { 0x4e50, R_350, "RV350 [Mobility Radeon 9600 M10]" },
+ { 0x4e51, R_350, "M10 NQ [Radeon Mobility 9600]" },
+ { 0x4e52, R_350, "RV350 [Mobility Radeon 9600 M10]" },
+ { 0x4e53, R_350, "M10 NS [Radeon Mobility 9600]" },
+ { 0x4e54, R_350, "M10 NT [FireGL Mobility T2]" },
+ { 0x4e56, R_350, "M11 NV [FireGL Mobility T2e]" },
+ { 0x5b60, R_370, "RV370 5B60 [Radeon X300 (PCIE)]" },
+ { 0x5b62, R_370, "RV370 5B62 [Radeon X600 (PCIE)]" },
+ { 0x5b64, R_370, "RV370 5B64 [FireGL V3100 (PCIE)]" },
+ { 0x5b65, R_370, "RV370 5B65 [FireGL D1100 (PCIE)]" },
+ { 0x3e50, R_380, "RV380 0x3e50 [Radeon X600]" },
+ { 0x3e54, R_380, "RV380 0x3e54 [FireGL V3200]" },
+ { 0x3e70, R_380, "RV380 [Radeon X600] Secondary" },
+ { 0x4a48, R_420, "R420 JH [Radeon X800]" },
+ { 0x4a49, R_420, "R420 JI [Radeon X800PRO]" },
+ { 0x4a4a, R_420, "R420 JJ [Radeon X800SE]" },
+ { 0x4a4b, R_420, "R420 JK [Radeon X800]" },
+ { 0x4a4c, R_420, "R420 JL [Radeon X800]" },
+ { 0x4a4d, R_420, "R420 JM [FireGL X3]" },
+ { 0x4a4e, R_420, "M18 JN [Radeon Mobility 9800]" },
+ { 0x4a50, R_420, "R420 JP [Radeon X800XT]" }
+};
+
typedef struct {
CoreSurface *source;
CoreSurface *destination;
DFBSurfaceBlittingFlags blittingflags;
+ __u32 chipset;
+
/* store some Radeon register values in native format */
__u32 RADEON_dp_gui_master_cntl;
__u32 RADEON_color_compare;
diff -urN ./DirectFB/gfxdrivers/radeon/radeon_overlay.c ./DirectFB.test/gfxdrivers/radeon/radeon_overlay.c
--- ./DirectFB/gfxdrivers/radeon/radeon_overlay.c 2004-11-20 23:18:08.000000000 +0200
+++ ./DirectFB.test/gfxdrivers/radeon/radeon_overlay.c 2005-07-05 08:15:42.000000000 +0300
@@ -432,6 +432,24 @@
/* reset overlay */
radeon_waitidle(rdrv, rdev);
+
+ if(rdev->chipset == R_100 || rdev->chipset == R_120 || rdev->chipset == R_150)
+ {
+ radeon_out32( mmio, OV0_LIN_TRANS_A, 0x12A00000);
+ radeon_out32( mmio, OV0_LIN_TRANS_B, 0x199018FE);
+ radeon_out32( mmio, OV0_LIN_TRANS_C, 0x12A0F9B0);
+ radeon_out32( mmio, OV0_LIN_TRANS_D, 0xF2F0043B);
+ radeon_out32( mmio, OV0_LIN_TRANS_E, 0x12A02050);
+ radeon_out32( mmio, OV0_LIN_TRANS_F, 0x0000174E);
+ } else {
+ radeon_out32( mmio, OV0_LIN_TRANS_A, 0x12a20000);
+ radeon_out32( mmio, OV0_LIN_TRANS_B, 0x198a190e);
+ radeon_out32( mmio, OV0_LIN_TRANS_C, 0x12a2f9da);
+ radeon_out32( mmio, OV0_LIN_TRANS_D, 0xf2fe0442);
+ radeon_out32( mmio, OV0_LIN_TRANS_E, 0x12a22046);
+ radeon_out32( mmio, OV0_LIN_TRANS_F, 0x0000175f);
+ }
+
radeon_out32( mmio, OV0_SCALE_CNTL, SCALER_SOFT_RESET );
radeon_out32( mmio, OV0_EXCLUSIVE_HORZ, 0 );
radeon_out32( mmio, OV0_AUTO_FLIP_CNTL, 0 );
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