Hi there.
It's been quite a while I have worked on it, I will tell you based on what I remember. Since VTA is made using HLS, I have looked at how HLS translates the VTA and makes those Verilog files. Using that information, I have put debug flags on that Verilog file synthesized by HLS. Since the Pynq-Z1 had so limited resources, I have ported into ZCU104 to do so. --- [Visit Topic](https://discuss.tvm.apache.org/t/vta-question-about-vta-hls-design/3858/18) to respond. You are receiving this because you enabled mailing list mode. To unsubscribe from these emails, [click here](https://discuss.tvm.apache.org/email/unsubscribe/99df60887b973df7723be9acccfd30974ddb8307cadae630e3e19f97e3a60682).
