The GitHub Actions job "Lint" on tvm.git/fix/cuda-min-max-nan has failed. Run started by GitHub user LngelKyo (triggered by LngelKyo).
Head commit for run: 5d7a3a02fd19f29fa6cdab1b3fc797a9a68749cb / LngelKyo <[email protected]> [Fix][CUDA] NaN-preserving min/max for CUDA: scalar, vector, and constant operands Match the C host semantics of apache/tvm#20054 for tirx.min/tirx.max on float16/bfloat16/float32/float64: - NaN-preserving ternary: ((a cmp b) || (a != a)) ? a : b — a NaN on either side is kept instead of being dropped by the bare min()/max(); - scalar operands are bound once via SSA inside their own scope (BeginScope/EndScope): SSAGetID caches by printed text and the base BufferStore dispatch does not invalidate it, so unscooped bindings read pre-write values when warp allreduce emits red_buf[0] = max(red_buf[0], shuffle_down(...)) repeatedly; - integer and other non-float min/max keep the base CodeGenC path, including the per-lane vector expansion; - constant operands follow #20054's min_max_utils.h: a constant NaN operand is printed directly as the surviving operand, a constant non-NaN operand lets the ternary drop its NaN clause (lhs non-NaN keeps the ordered compare, rhs non-NaN reverses to a non-strict compare: < -> >=, > -> <=); the constant side is not SSA-bound; - float64 included so CUDA matches the C host. Tests in test_target_codegen_cuda.py (gpu-marked, nvcc/nvrtc via the autouse fixture): #20054 data bitwise across 4 dtypes x 2 ops x {scalar, vec4}; composite nesting (max(a, b) + 1.0, NaN lanes assert NaN); chained statements reading the same text with a write in between (fails pre-fix); int32 vec4 regression vs numpy; constant-operand cases (#20054's test_min_max_float_imm_operand data), 32 cases. Partially addresses #19579 (CUDA side); host side is #20054. Report URL: https://github.com/apache/tvm/actions/runs/35669519272 With regards, GitHub Actions via GitBox --------------------------------------------------------------------- To unsubscribe, e-mail: [email protected] For additional commands, e-mail: [email protected]
