Hi to everybody.
I am new in Electric. I am try to convert a simple vhdl code to a
netlist. For example, this one of an or gate:
library ieee;
use ieee.std_logic_1164.all;
entity OR_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end OR_ent;
architecture OR_arch of OR_ent is
begin
process(x, y)
begin
if ((x='0') and (y='0')) then
F <= '0';
else
F <= '1';
end if;
end process;
end OR_arch;
architecture OR_beh of OR_ent is
begin
F <= x or y;
end OR_beh;
So i made a vhdl cell and i put the code in it. After i try to use
Silicon Compiler from Tools but all my code its full of errors.
TOO MANY ERRORS...PRINTING NO MORE
ERRORS during compilation, no netlist produced
Can someone help me.
Thanks
Chris
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