> I've been through the Wiki but haven't been able to sort > this out. What's involved in driving the USRP from an > external clock?
Remove X2, add J2001. Feed J2001 a CMOS-level clock. The clock you send in will be your ADC sampling clock. Your DAC sampling will be 2X the frequency you send in. Your clock should be less than or equal to 64 MHz. The FPGA will operate at your clock rate unless you make changes to the FPGA design to use the internal PLLs. Matt _______________________________________________ Discuss-gnuradio mailing list [email protected] http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
