Quoting Robert McGwier <[EMAIL PROTECTED]>:

> I would like to do N, where N is larger than 4, correlators on the FPGA
> in order to do code acquisition for code division multiplexing.  I would
> also
> like to do beam steering experiments on four channels.  All involve
> multiplications and the lower the latency, the better.
>
> Then the question becomes how MUCH ram is burned in this scheme?  Is it
> onerous?  We are not anywhere near the fill up point in the Cyclone yet
> are we? Can we get a link to this paper instead of just an announcement?


Everything you mention should be doable.  Another thing to keep in mind is that
you can rip out various parts of what is currently in there if you don't need
them.  For example, a receive-only application can save quite a bit of space by
removing the TX stuff.  Also, if you are doing a correlator, you may want to
integrate the carrier tracking with it.  In that case, you would probably take
out the DDCs that are in there now.

Matt


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