Matt Ettus wrote:
David P. Reed wrote:
In interfacing a new 5 GHz up/downconverter to the USRP (my summer
project), I find that I need a 40 MHz frequency reference to drive a PLL
in the chip. My first prototype will interface using the Basic Rx/Tx
daughterboards, and it occurs to me that I can probably use one of the
DAC clocks for that.
Should this work? Any other suggestions (at this stage I'd prefer to use
an existing, programmable source on the USRP, rather than another chip
and crystal)?
Does it need to be 40 MHz? 40 is going to be hard to produce cleanly on
the board. 128 divided by any integer is much easier.
Matt
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Sounds like a nice summer project :-) 40 MHz seems to be a standard TCXO
frequency, based on a quick perusal of the Digikey catalog. It would be
a single part to add to the board. If this is used as a reference
oscillator for a PLL, then you might be better off from a performance
point of view by adding the part and getting a clean reference. Your
spurious emission's specification's will thank you.
Digitally, you could multiply the 128 by 5 to get 640 MHz, and then
divide by 16 to get 40 MHz, but I don't think you could do this in the
FPGA.
Dave
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