On Fri, Jul 22, 2005 at 05:11:35PM -0700, Eric Blossom wrote: > On Sat, Jul 23, 2005 at 04:35:05AM +0500, Ahmad Sheikh wrote: > > > > But using usrp.source_c().set_pga() means that the feedback control > > be on the python level, which would mean that there would be a large > > latency in the gain control. Isn't there some way to do this on the > > hardware? > > -Ahmad > > The PGA is controlled over the SPI serial bus from the FX2 (as are all > the AD9862 registers). You could hack the FX2 firmware to control it, > but I'm not sure how you'd make the measurement.
If you're willing to design/write/debug/test Verilog, there's nothing
stopping you from changing gain from the FPGA. I have done something
equivalent on an XC2S200 (sending live data out to a DAC using an SPI
bus. It's a non-trivial amount of work, and it really helps to know
what you're doing.
- Larry
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