On Thu, Aug 25, 2005 at 04:39:27PM -0400, cswiger wrote:
> On Thu, 25 Aug 2005, Martin Dvh wrote:
>
> Oh, the docs in usrp1_sink_base.h and usrp1_source_base.h point
> out that in set_tx_freq and set_rx_freq the channel must be 0.
> So it looks like all DUC and DDC must be at the same frequency.
On the rx side, channel can be 0 or 1 (0,1,2 or 3 with 4 DDCs in FPGA,
but the standard build only has 2).
On the tx side there are only two channels, 0 or 1 (1 for each 9862 -- see
previous message about "tx mux explained").
All the DUCs and DDCs frequencies are independent of each other.
[The docs in usrp_basic.h, usrp_standard.h rule. I'd welcome a patch
that updated the docs in usrp1_{sink,source}_base, or better yet a
tool that copies the relevant docs from usrp_{basic,standard}.h to
usrp1_{sink,source}_base so that this documentation-rot doesn't keep
coming back.]
Eric
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