On Tue, Oct 25, 2005 at 02:44:51AM +0200, Martin Dvh wrote: > Hi, > I want to enable sync input and output pins and are looking for where the > these should be set. > In my search for examples, I looked for the place where the output is > enabled for the 4Mhz reference clock, which is output on io[0] for some > daughterboards, like the dbsrx. > > But I can't seem to find where this output is enabled.
Secret's revealed!! The daughterboard handling code sets it. See db_flexrf.py for example usage. Search for refclk >From fpga_regs_standard.h: // Control whether a reference clock is sent to the daughterboards, // and what frequency // // Bit 7 -- 1 turns on refclk, 0 allows IO use // Bits 6:0 Divider value #define FR_TX_A_REFCLK 40 #define FR_RX_A_REFCLK 41 #define FR_TX_B_REFCLK 42 #define FR_RX_B_REFCLK 43 We really ought to machine generate the python equivalent. We already generate a verilog equivalent. Eric _______________________________________________ Discuss-gnuradio mailing list [email protected] http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
