On Thu, Nov 10, 2005 at 06:23:57PM -0500, cswiger wrote:
> This should be simple: a 2nd basic-RX board plugged into J668
> works with a siggen, and scope w/ mux=0xf0f0f0f2, nchannels = 2
> shows adc0 and adc2 A-OK. So the hardware is working fine.
> 
> But when I try to use it in my script I get a flatline:
> 
>         # setup usrp
>         decim = 64
>         self.dut_out = usrp.source_c(0, decim, 4, gru.hexint(0xf0f2f1f0),
> 0)
>         self.dut_out.set_rx_freq(0,-self.f_ducddc)
>         self.dut_out.set_rx_freq(1,-self.f_ducddc)
>         self.dut_out.set_rx_freq(2,-self.f_ducddc)

The FPGA contains only 2 instance of the DDC, not 4, hence your problem...

Eric


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