On Tue, Jan 17, 2006 at 02:01:37PM -0500, Michael Dickens wrote:
> Eric - We do have a logic analyzer, but with the basic connectors.
> Thus we'd think about changing the FPGA code to route the usbctl[]
> signals to a daughtercard for viewing. I can tell that at least 2 of
> the files you're referring to are:
>
> "usrp/fpga/toplevel/usrp_std/usrp_std.v"
> "usrp/fpga/sdr_lib/master_control.v"
>
> Unfortunately I'm not an FPGA programmer, and what you wrote (below)
> doesn't help me very much, even looking at those files and rereading
> a few times over. Is there maybe another way you could explain it
> which would be more enlightening? I'd rather believe that I'm at
> least 90% correct in my changes before messing around and possibly
> breaking something ("be careful!"). Thanks! - MLD
Actually, you'll be able to look at the RD line without changing
anything in the FPGA. More details in a bit.
Eric
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