On Wed, 2006-04-05 at 10:16 -0700, Eric Blossom wrote:
> I moved it all to a new module, gr-atsc in CVS.
>
> It's already autoconfiscated and ready to go. There's a file,
> README.signal_flow in the top level directory that tells how the old
> code was connected together. There are loopback tests for the first
> two blocks in each direction in the python directory.
>
> The normal:
>
> ./bootstrap
> ./configure
> make && make check && make install
>
Ok, found it - If I understand correctly, it looks like the next block
to finsh is the convolutional interleaver, and it's reverse the
convolutional de-interleaver.
Existing 2.0 layers:
--------------------
Src (mpeg transport) Dst
v ^
Randomizer Derandomizer
v ^
Reed-Soloman Encoder -----> RS Decoder
Yet to be done:
---------------
v ^
Convolutional Interleaver -> De-Interleaver
v ^
Trellis Encoder -> Viterbi Decoder
v ^
Field Sync Multiplexor -> Field Sync Demux
v ^
Symbol Mapper Equalizer
v ^
Weaver Modulator Head Field Sync Checker
v ^
FIR Filter (lp root raised cosine) Bit Timing Loop3
v ^
Weaver Modulator Tail Remove DC
^
| FIR Filter, Image Remove
| ^
| FPLL Carrier Tracking PLL
| and down converter
| IF ^
+-----------------> FIR Filter (lp root raised
cosine)
Actually the FIR filters already exist, as does the carrier tracking
PLL and mixer. Since we start with a complex source already (usrp
in place of the mc4020 'short' data source) image removal won't be
necessary (I guess). So really all we need is the logic from 6 blocks
repackaged for a receiver, and 6 for a transmitter to do stage-by-stage
testing. IIUC.
--Chuck
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