On Thu, Apr 06, 2006 at 06:55:57PM +0200, Martin Dvh wrote:
>
> (Life would be so much easier if all the clocks on the usrp would first go
> through the fpga.
> Which could then upconvert/divide/pll/override/combine any clock in verilog
> software.)
Rule 1 for digitizing RF: never let the clock touch the FPGA.
Even if the chip itself were perfect, all that package-induced
ground noise spells death to any decent phase noise performance.
- Larry
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