Some notes on the data pipeline and buffering: Max length USB2 packets are 512 bytes, and that is all that we use.
The FIFOs in the FPGA are each 8192 bytes (16 packets), one for TX and one for RX. This is limited by the RAM in the FPGA. At full data speed of 32 MB/s over the USB, this is 256 uS worth of buffer. The buffering in the USB controller chip is 2K bytes each for in and out, or 4 packets worth. The interface between the FPGA and the FX2 will only transfer full 512-byte chunks. On Sun, 2006-05-07 at 12:15 -0400, Greg Troxel wrote: > 1) Is the USB transaction size fixed by the USRP firmware? Is it > happy with a range of sizes? Fixed by several factors. > > 2) Does the USRP ever send a short transaction on read? Are there > start/stop issues? No. > 3) Has an optimal transaction size been determined? This seems to be > a latency/efficiency tradeoff, but the amount of on-board buffering > seems key. No, we haven't looked into short packets for better latency. Matt -- Matt Ettus <[EMAIL PROTECTED]> _______________________________________________ Discuss-gnuradio mailing list [email protected] http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
