On Wed, Jun 07, 2006 at 07:04:00PM +0200, Kilian Timmler wrote: > Ouch! > > This sounds like some of those previous threads. > > >Why do you want 16MS/sec real instead of 8MS/sec complex? > > > >Eric > > I didn't want to go there, the part I was worried about is to have no > processing > since the CIC filter has some unpleasant properties (not very flat, aliasing > at the borders).
The final stage of the 8MS/sec path is run through a halfband filter and thus is pretty flat. That is, the final decimation-by-two is performed using a 31-tap halfband, not a CIC. > From my point of view the PC is much more accessible than the > FPGA. To get an understanding of the algorithms I don't have to try > to read someones Verilog code, and to change any algorithms I don't > have to write Verilog. On the other hand the PC should be quite > capable in handling most signal processing tasks. Yep. > I'm generally interested in working with FPGAs but I don't have a > logic analyzer, so that actual experiments might be cumbersome. Simulation goes a long way. Or just "get it right" the first time ;) See also icarus verilog. > Anyway, I saw today that there is an fpga version with a halfband > filter now, very nice. Eric _______________________________________________ Discuss-gnuradio mailing list [email protected] http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
