hanwen wrote:
Hi,
Recently, I'm trying to do CDMA commnication at 1.28Mchip/s with USRP
and I've met a problem.
The sample rate of DAC on USRP is 128M, so samples avialabe for each
chip is 128M / 1.28M = 100.
The interpolation rate of USRP must be [4, 512] and multiple of 4. So
the only choice for me seems to be setting the software interpolation
rate to 5 and the interpolation rate of USRP to 20 (multiple of 4). 5
* 20 = 100. But the software interp is still too high for the
root_raise_cosin interp filter (interp=5, len(taps)=16), and a lot of
"Uu" comes out. However, the software interp cannot be reduced further.
I wonder if the sample rate of DAC can be change to mutiple of 2, not
4. In that case, I can set the software interp rate to 2 and interp
rate of USRP to 50, for which the burden of interp filter can be reduced.
With the current FPGA build, the interpolation must be a multiple of 4.
If you wanted to go to the effort, you could build your own version
which would:
- have the digital upconverter in the FPGA instead of using the one in
the AD9862
- run the data to the AD9862 at 128 MHz instead of 64
Right now, I have to use 1.3333Mchip/s. The software interp rate of 2
works well. But 1.28Mchip/s is exactly what I want.
You might be better off using an external clock into the USRP which is a
more convenient multiple.
Matt
_______________________________________________
Discuss-gnuradio mailing list
[email protected]
http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
