On Tue, Aug 01, 2006 at 01:43:29PM -0700, Oussama Sekkat wrote:
> Hi,
> I am looking at the tx_buffer module. From my understanding, that module
> does the interlacing of the data to be transmitted (2 I channels and 2 Q
> channels). Is that correct?

It implements the transmit direction part of the FX2/FPGA GPIF
interface.  It also demuxes the data to be transmitted and sends it to
the appropriate DACs.

> Also, next to the bus_reset input declaration there is a comment saying
> "Used here for the 257 hack to fix the FX2 bug". Which bug is it talking
> about?

On the FX2, the WR pulse is asserted one clock longer than it should be.  

Eric


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