Hi
I was doing some tinkering with the Verilog code, especially in the tx_buffer module. I'm experimenting with trying to replace the FIFO in the tx_buffer module with a quartus generated altsyncram module. I want to see if I can trap the incoming signal and control when it's released. I tried the following:
signal_ram signal_ram
( .data ( usbdata ),
.wren ( WR & ~write_count[8] ),
.wrclock ( usbclk ),
.wraddress ( wrptr ),
.q ( ramdata ),
.rden ( rdreq ),
.rdclock ( txclk ),
.rdaddress ( rdptr ),
.wr_aclr ( reset ), // asynch, so we can use either
.rd_aclr ( reset ),
);
When I experiment with transmitting a signal from the pc, then the program hangs without transferring any bytes. I suspected that perhaps the write enable (wren) for my ram block wasn't functioning as I thought. Have I used it properly here to enable writing to ram, or is there something I've missed?
Regards
Lance
I was doing some tinkering with the Verilog code, especially in the tx_buffer module. I'm experimenting with trying to replace the FIFO in the tx_buffer module with a quartus generated altsyncram module. I want to see if I can trap the incoming signal and control when it's released. I tried the following:
signal_ram signal_ram
( .data ( usbdata ),
.wren ( WR & ~write_count[8] ),
.wrclock ( usbclk ),
.wraddress ( wrptr ),
.q ( ramdata ),
.rden ( rdreq ),
.rdclock ( txclk ),
.rdaddress ( rdptr ),
.wr_aclr ( reset ), // asynch, so we can use either
.rd_aclr ( reset ),
);
When I experiment with transmitting a signal from the pc, then the program hangs without transferring any bytes. I suspected that perhaps the write enable (wren) for my ram block wasn't functioning as I thought. Have I used it properly here to enable writing to ram, or is there something I've missed?
Regards
Lance
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