Lin Ji wrote:
Hi,
There is one thing that I can not figure out:
The ADC on the USRP has a sampling rate at 64Msps, that is, for a
data at 1Mbps, for every incoming bit there will be 64 samples.
Suppose every sample is 16bits, the bit rate is 1024Mbps,that is a
huge amount of data flow. Now if a user want to same these samples to
file through USB, even though the USB 2.0 interface has a high
throughput at 480Mbps, it's not enough. If there is a buffer(like a
FIFO or something) that is handling the ADC to USB tranfer, sooner or
later this buffer will get full, how is this situation been handled?
Thanks.
/Lin
Data is decimated using a CIC filter implemented in the FPGA. Data is
sampled on the front-end at 64MSPS and then the signal is filtered and
decimated (sample rate is reduced by dropping a number of samples) to
point that can be handled by the USB 2.0 bus (32 MBytes/Sec). If you
have a complex 16-bit data stream, you have 16-bit In-phase, 16-bit
Quadrature; therefore, you have 4 bytes per complex sample. It is stated
that only 8 MSPS (complex samples) can be sent across the USB bus and
this corresponds to 8 MSPS * 4 bytes = 32 MBytes/Sec. In other words,
you have to decimate you front-end 64 MSPS signal by a minimum of 8and
this gives you 8 MHz of bandwidth; of that, it is stated that only 6 MHz
or so is usable due to wrapping/aliasing from the filter roll-off.
32 MBPS becomes 32 MBPS * 8 bits/byte = 256Mbps ; which is little more
than 50% of the theoretical max.
--Ryan
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