On 3/1/07, seph 004 <[EMAIL PROTECTED]> wrote:

 This is what I did:

def build_graph ():
    nchan = 1
    interp = 512
    duc0 = 0
    duc1 = 0
    fs = 250e3                                        #2nd sample rate
between usb and dac
    max_dev = 32e3                              #1st sample rate divided
by 4 (1st = 2nd sample rate)
    gain = 16e3
    k = 2 * math.pi * max_dev / fs
    vec1 = Numeric.arange (0.624, 0.656, 0.0000128)
    vsource = gr.vector_source_f(vec1, False)
    fmmod = gr.frequency_modulator_fc (k)
    amp = gr.multiply_const_cc(gain)

    fg = gr.flow_graph ()

    u = usrp.sink_c (0, interp, nchan)
    tx_subdev_spec = (1, 0) #usrp.pick_tx_subdevice(u)
    m = usrp.determine_tx_mux_value(u, tx_subdev_spec)
    u.set_mux(m)
    subdev = usrp.selected_subdev(u, tx_subdev_spec)
    subdev.set_enable(True)

    sample_rate = u.dac_freq () / interp
    u.set_tx_freq (0, duc0)
    u.set_tx_freq (1, duc1)


Are you trying to use one daughter boards(nchen=1)?   Why did you set duc0 =
0?   that means your  frequency will not be set at all.  You do not need to
do set_tx_freq() twice if you are using one daughter board.  you only need :
u.set_tx_freq (0, duc0) where duc0 is some frequency.  Also, if you are
using the basic daughterboards, you need to make sure that you have the
output connector connect to TXA not TXB (according to your tx_subdev_spec)


Hope this helped.

David
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