On 3/6/07, Davide Anastasia <[EMAIL PROTECTED]> wrote:
I tried this test bench, but I guess it doesn't work. Infact, I test the
bit_pack module obtaining a strange output file like the attached one.
Any suggestion from the list and/or Verilog Guru? :)
It looks like you possibly have multiple sources on your signals which
conflict with each other.
Only one process can assign to a wire.
I use iverilog on my Ubuntu 6.06 workstation.
Regards,
--
Davide Anastasia
web: http://www.davideanastasia.com/
email: [EMAIL PROTECTED]
Brian
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