Peter Monta wrote:
Could FPGA jitter be contributing? It can be hundreds of picoseconds,
but whether there would be low-frequency content in the jitter spectrum
I don't know.
FPGA jitter might be contributing, but there shouldn't be much at low
frequency. You could try measuring this by sending a clean carrier from
a signal generator into the DBSRX and looking at the phase noise on the
received signal.
Should I try moving the R193/R194 resistor on the dbs_rx
to select clock_p (which is apparently a clean 64 MHz feed from the clock
chip)? The MAX2118 data sheet says 27 MHz max, but maybe that's just
for the crystal oscillator, and the reference divider might be okay with
a higher external frequency.
You can try that -- only if you have a rev 4 or higher USRP. If 64MHz
is too high for the MAX2118, you could experiment with making the clock
generator chip (AD9513) give you a 32 or 16 MHz clock. You would need
to change around some of the tiny resistors on the back of the USRP
motherboard -- see clock.sch and the AD9513 datasheet for how to do this.
Matt
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