You will have to calibrate _everything_ in the path, and of course
that includes the signal processing in the FPGA as well as anything in
the host-based signal processing path.  And yes, pretty much all of
this varies depending on a large variety of settings.  E.g., you'd
want to calibrate for each possible FPGA decimation rate that you're
interested in.

As long as you stick to power of 2 decimation, you don't need to calibrate for different settings.

Matt


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