Brian Padalino wrote:
Looks cool to me.
32-bits should be OK. What problems do you think you may have an issue
with?
None particularly. There is no 32 bits wide bus in the fpga currently,
so I thought that it might use too many connections.
You will probably have to create your own FIFO from the lopsided RAM.
I don't think there is a way to infer a RAM where side A is a
different size than B. The skip functionality is pretty straight
forward, and you probably just need empty and full flags. That
shouldn't be difficult.
Ok.
They have a version of ModelSim you can download and use the Altera
blocks all for free. I'd recommend just using that and not going
through the Altera tool. Write a normal testbench and test out that
FIFO.
I'm downloading it :) .
If you need me to verify any results or help with any of your coding,
just ask. I have ModelSim along with the Altera tools available to
me.
Thanks. I'm sure I will need your expertise.
Brian
Thibaud
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