Hi, I want to control I/Q signal going through USRP by the path of DEMOD->RX->FPGA->TX->MOD, quite similar to what have been done by Jon Jacky in the following presentation:
http://www.research.cornell.edu/KIC/events/MRFM2006/pdfs/Jacky%20talk/jacky-talk.html The main different is that I'm going to use I/Q signal from analogue DEMOD instead of doing the digital demodulation. I've been thinking about the easiest way on how to achieve this aim. Do I need to program the FPGA using Verilog or can I just get away with higher level C++/Python code? How about the delay for the processing, is it possible to get less than 1 us delay? Regards, Shaiful Hashim, Cardiff School of Engineering, UK ____________________________________________________________________________________ The fish are biting. Get more visitors on your site using Yahoo! Search Marketing. http://searchmarketing.yahoo.com/arp/sponsoredsearch_v2.php _______________________________________________ Discuss-gnuradio mailing list [email protected] http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
