On Thu, Apr 19, 2007 at 05:17:06PM -0400, George Nychis wrote:
> I'm starting to work out some test code regarding the host end, and I was
> wondering how hard it will be when done testing to actually put a packet on
> the bus? I assume we can reuse some of the previous interface.
Not very hard.
> Question from Thibaud: is the loopback interface working on the USRP, and
> how to enable it?
There is a loopback interface in the current FPGA code. It's enabled
by writing to the FR_MODE register. Grep the verilog for "loopback",
and look at fpga_regs_common.{h,v}
> We want to test out using the loopback eventually, and overall I'm
> wondering how much time from when I finish the test code to putting a
> packet on the interface so I can plan out this week. :)
I don't know. When will you have the rest of the host code written?
I suggest that you treat this like it's "your project", not "Eric's
project". I'm available to answer questions, respond to requests,
etc., but don't assume that the cavalry is coming ;)
What's your next step?
I'm working on mblock timeouts ;)
Eric
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