I have also noticed the "flipping" , but not when transmitting only when
restarting, the signal flips 90 degree.
but this only happens when using the subdev, when using gr.sig_source_c
this
doesn't happen.
I couldn't see why this only happens with subdev.
I had similar problems during receive. It appears that one I or Q sample
was getting lost so the remaining I and Q samples appeared to be reversed.
The problem only occurred when I was using usrp._read_fpga_reg() to poll the
rssi register.
-- Don W.
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