Brent M. Ledvina wrote:
> Hi,
>
> I am running into a USB bandwidth issue. I'm sampling data
> simultaneously from 2 daughter boards at a decimation rate of 10. This
> produces 2*6.4 MS/s * 4 bytes/I and Q sample = 48 MB/s.

Actually, the correct calculation of data rate is:

6.4 MS/s * 2 * 2 = 25.6MB/s

One factor of 2 is for I and Q.  The other is for 2 bytes per sample,
since 16 bit samples are sent over the USB.  They are converted to
floats on the host computer.

> My application requires one board to have a decimation rate of 10, but
> the other can have a decimation rate of ~30. My understanding of the
> USRP is that you cannot easily (i.e. in software) use different
> decimation rates for different daughter boards on the same USRP. My
> questions are: 1.) Is this easy to do at the FPGA level? 2.) Has
> anyone tried this before?

It is not possible with the default FPGA build to use different rates
for 2 RX streams.  The TX and RX can have different rates though.

Matt



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