Thank you Brian and Mande. >> Something you may want to try to do is focus on the TX side of things. >> >> RX is generally the harder part of radio communications, and probably >> wouldn't work out too well inside of an FPGA that is already pretty >> full. TX on the other hand is all just simple permutations, look up >> tables, and maybe some filtering to stay within band. >> >> You can probably write a decent M-QAM mapper, convolutional encoder, >> interleaver, etc and not have it take up too much room other than some >> registers and block rams. If you wanted to get more complex, a GMSK >> mapper might also be interesting. >> >> An interesting consequence of doing this is that your TX bandwidth >> goes significantly down since you don't have to pump 16-bit I/Q values >> over the bus, just your raw data rate. This allows for a USRP setup >> to both TX and RX to have more USB bandwidth dedicated to the real >> processing (RX) and not just some LUTS (TX). >> >> Brian
I have been tracking this topic for sometime now. I am working on a similar problem. Would it be a better idea to use a Reed Solomon encoder ( http://www.opencores.org/projects.cgi/web/rsencoder/overview) and Reed Solomon decoder ( http://www.opencores.org/projects.cgi/web/rs_decoder_31_19_6/overview ) from OpenCores.com to start with? It might be interesting to make it work with the USRP. Both the encoder and the decoder are written in Verilog and are in Production/Stable stage. I have just started to work with USRP and any help on the above topic would be helpful to me. Thanks. Dhaval.
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