Thank you Brian ! You have been a great help !
-S. Mande On 9/11/07, Brian Padalino <[EMAIL PROTECTED]> wrote: > > On 9/11/07, S Mande <[EMAIL PROTECTED]> wrote: > > Hi, > > > > > > I scanned the Mailing List Archive and figured out that the code that > goes > > inside USRP FPGA is Verilog code. > > > > I personally know VHDL and was looking to make some changes to the FPGA > > code. > > > > I was wondering if it is possible for the existing (USRP's) Verilog and > my > > VHDL code to co-exist ? If yes, than do I need to make some special > changes > > to the existing USRP Verilog code for both to coexist? > > Quartus can do mixed-mode synthesis meaning you can have both VHDL and > Verilog code as long as they are in different modules. You will want > to read exactly how Quartus does it all, but it is in fact possible. > > > Or would it be advisable to code my new module in Verilog only? > > It is advisable to just learn the Verilog. VHDL is a much more > difficult language to understand due to the strict typing rules. If > you can understand and write synthesizable VHDL, picking up Verilog > should be a snap. > > In summary: you can write VHDL if you want to deal with the headaches > associated with it, but learning Verilog (since you already know VHDL) > should be much easier and produce a lot less headaches. > > Brian >
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