Hi,
I am using the TV_RX and USRP to capture the 64 Msps data from the A/D converter and send that to another downstream board for processing. I am connecting the signal from the ADC to the debug IO pins of the FPGA to get to the 16 io_rx[] pins of Basic RX. However, my board-to-board interconnection turned out to have a bandwidth limitation of 50 MHz so I can no longer hope to send 64 Msps raw data from the ADC over the interconnect bus. The next best thing would be to decimate by a factor of 2 and then route the 32 Msps data to the debug pins. I understand the the CIC has a decimation range of [4,5,6,.128] and the HBF decimates by a factor of 2. Is there a way to get an overall decimation of just 2 by possibly bypassing the CIC and using only the HBF? If this sounds like a dumb question then, what would be the best way to get 32 Msps over to the Basic RX card using what's already in the FPGA? Thanks in advance for any suggestions. Nirali
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