Hello, I have been trying to understand the tx and rx data paths through the AD9862 and the FPGA (standard configuration).
RX side: - The two ADCs of the AD9862 push data onto two 12 bit buses - After the FPGA MUX the 16 bit I/Q signals pass into the assigned DDC - Are four extra bits assigned to the received I/Q when they arrive onto the FPGA? TX side: - The 16 bit I/Q signals pass into the FPGA demux and arrive at the appropriate AD9862 chip - I/Q signals arrive interleaved on a 14 bit bus into the AD9862 - Are the I/Q signals truncated by 2 bits before they are sent onto the 14 bit bus? Thanks, Tomas -- View this message in context: http://www.nabble.com/Bus-widths-and-data-rates-tp15145586p15145586.html Sent from the GnuRadio mailing list archive at Nabble.com. _______________________________________________ Discuss-gnuradio mailing list [email protected] http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
