On Tue, May 20, 2008 at 9:38 PM, Charles Swiger <[EMAIL PROTECTED]> wrote:
> The issue turned out to be jiggering the numbers that say "I strongly
> suggest that you not mess with these..." * by .707 for the bit timing
> loop worked ;)
>
> We want a complex pll so it can take data directly from the usrp
> centered on DC, w/o having to mix it up to 5.75e6 and converting to
> real for the old fpll, which was just a trick to look like the old
> mc4020 adc boards.
Sorry, Chuck. I am still not sure I understand the whole deal. I am
not even sure how a PLL is being used since it's all AM and there's no
real phase information being transmitted - is there?
I was starting to read this:
http://www.broadcast.net/~sbe1/8vsb/8vsb.htm
And it just made me more confused as to what you're trying to
accomplish using complex operations on a signal where the lower
sideband has been filtered away.
Any more help?
Thanks,
Brian
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