Brian Padalino wrote:
On Fri, Aug 8, 2008 at 2:14 PM, yyzhuang <[EMAIL PROTECTED]> wrote:
Hi all,
Because if USB, USRP is limited in bandwidth. So do you know when USRP2 is
coming out please? Thanks.
Just wondering - how much bandwidth do you need?
If you are going to run with a fixed amount of decimation for all of
your tests, you can change the FPGA's CIC to have a fixed value and
bypass the halfband filter if you want. This will free up a
SIGNIFICANT amount of space in the FPGA to perform filtering,
equalization, and other processing.
The default build allows for some serious decimation, and a LOT of
options for general SDR. For more specific purposes, use the sdr_lib
to your advantage, make your custom chain, and write the rest of your
custom FPGA load.
I am no expert, but I believe the USRP samples 4 real or 2 complex
channels at 64MHz. Is there reason to believe this is not enough
bandwidth?
Brian
I could make use of 30 MHz in a single channel at 14-bit resolution; in
other words - all the USRP2 may offer plus a little (but we will use a
trigger to select a portion of data at timed intervals - so the USRP2
will provide what we need). So yes, for our needs, there is reason to
believe that this will not be enough.
Ryan
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