Matt My DSPing is a bit rusty. With the TVRX card, we send -20MHz to the DDC. Is this because of 44-64 MHz? The code where the actual FPGA register gets written is in usrp_standard.cc? Here is a function called compute_fpga_freq_control_word which takes the -20MHz and returns 2952790016 which is 10110000000000000000000000000000 in binary. So for a DDC value of -20MHz, is that the value that gets written to the FR_RX_FREQ_0 register? What gets written to FR_RX_PHASE_0? Just zero? I'm just trying to figure out how the cordic and phase accumulator parts are implemented.
Thanks a lot. Sebastiaan _______________________________________________ Discuss-gnuradio mailing list [email protected] http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
