On Mon, Sep 08, 2008 at 04:49:23PM -0400, Brian Padalino wrote:
> 
> Problems arise when you want to ensure your FIFO is not full and not
> empty.  As a message passing mechanism, it works pretty well as just a
> DPRAM.  As the FIFO, there are counters involved which can cause
> timing issues when dealing with asynchronous clocks.
> 
> > I'm not even too concerned about the dual timestamp counters at the moment.
> > Is there any suspicion that they are ever unaligned?
> 
> If it's coming from two different parts of the chip with two
> independent reset signals, then yes there is always suspicion that
> they are unaligned.

That there ever were two counters was a bug.

Eric


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