Uwe Bonnes wrote:
Dear Matt or anybody else using USRP2,
can anybody give us the usage pattern of the USRP2 FPGA, e.g. what is needed by
the AEMB, by the Ethernet MAC, for signal processing and any other part
eating up a substantial part of the resources?
To get the number, Webpack isn't enough...
Keep in mind that the real constraint on what fits is actually Block RAM
-- we are currently using 37 out of 40 of them, and it is the reason we
had to move up to the 2000 part instead of the 1500. We have a huge
amount of extra logic (slices) and multipliers available for users. We
are currently using 16 out of 40 multipliers and less than 40% of the
~40,000 LUTs and Flops.
Item Slices BRAM
Eth ~2500 7
aeMB 1128 0
serdes 550 2
dsp_tx 2373 0
dsp_rx 2807 0
buffer pool 1416 8
rx sample fifo 2
tx sample fifo 2
main ram for proc 16
Matt
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