On Wed, Oct 1, 2008 at 3:43 PM, Eric Blossom <[EMAIL PROTECTED]> wrote:
> Excuse me if this is totally off the wall, but since if you run the
> verilog under a simulator (e.g., icarus), it will generate traces that
> give you all the state, on every clock. What's to model?
Verilog simulators can take a very long time to run for large data
sets. It might also be helpful in making sure signals sent down the
chain don't overflow or clip within the USRP.
Lucky for Kyle, there isn't much going on within the USRP. The
upconverters and downconverters are pretty standard and should be
easily modeled if there aren't models already in Octave.
Octave does have a fixed point toolbox. A quick google search revealed:
http://wiki.octave.org/wiki.pl?CategoryFixedPoint
A simple m-file should be able to accomplish the modeling.
Brian
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