On Wed, Oct 29, 2008 at 3:55 AM, Eric Blossom <[EMAIL PROTECTED]> wrote:
> On Wed, Oct 29, 2008 at 03:41:19AM -0700, Karthik Vijayraghavan wrote: > > I am trying to use the LFRX daughterboard to record very low frequency > > signals in the range of ~DC to about 10Hz. To test this I hooked up a > > function generator to the USRP with an output impedance of 50 ohm. Since > I > > wanted to get 4 channels simultaneously I loaded the "std_4rx_0tx.rbf" > image > > and looked at the signals after recording to a file. The daughterboard > seems > > to be having a DC blocking behaviour where the amplitude of received > signals > > decreases with lower frequencies. My rx gain is set to 0 and Vin = 1Vpp > with > > 0 DC offset. At 10Hz I get an amplitude of 400 from the ADC. At 1 Hz it > > drops to 40 and I get nothing at DC. I have tried fiddling around with > the > > gain, but it doesn't help much. > > > > This seems to be weird behaviour since the LFRX is supposed to work upto > DC. > > Am I missing something? I have read all the previous posts on this issue > and > > they weren't helpful for my problem. Any hints/directions would be > greatly > > appreciated. I have spent quite a bit of time on this can't figure out > the > > problem. > > > > Karthik > > Karthik, > > you'll want to turn off the ADC dc offset correction loop > that's running in the FPGA. (From usrp_basic.h) > > /*! > * \brief Enable/disable automatic DC offset removal control loop in FPGA > * > * \param bits which control loops to enable > * \param mask which \p bits to pay attention to > * > * If the corresponding bit is set, enable the automatic DC > * offset correction control loop. > * > * <pre> > * The 4 low bits are significant: > * > * ADC0 = (1 << 0) > * ADC1 = (1 << 1) > * ADC2 = (1 << 2) > * ADC3 = (1 << 3) > * </pre> > * > * By default the control loop is enabled on all ADC's. > */ > bool set_dc_offset_cl_enable(int bits, int mask); > > > In python, it's a method of usrp_source_*. > > Eric > Eric, Thanks, that worked! For archival purposes here is the piece of code that worked for me. It disables the DC offset correction from all 4 ADCs self.rx_src = usrp.source_c() self.rx_src.set_dc_offset_cl_enable(int(0),int(15)) I hooked up a 2Hz sine wave with no DC offset to the USRP and I see a rather large offset after the signal comes into the USRP. This offset value changes every time I run my program and remains constant during the course of the program. The offset is different for different ADCs / channels. I also measured an open circuit voltage of 106mV between the inputs of all the ADCs. Is this variable offset due to some registers not getting cleared when a program finishes running? Thanks, Karthik
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