Eric Blossom wrote:
On Wed, Jan 21, 2009 at 09:50:41PM -0500, Paul Creekmore wrote:
Eric Blossom wrote:
On Wed, Jan 21, 2009 at 05:47:19PM -0500, Paul Creekmore wrote:
Thanks for answering your own question :-)
The USRP1 is little endian. My not-fully-considered thought is that it
ought to go like this (everything packed into a 32-bit word):
16 bit I & Q (same as today):
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
| Q0 | I0 |
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
8 bit I & Q (different from today: see usrp_source_c.cc):
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
| Q1 | I1 | Q0 | I0 |
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
4 bit I & Q:
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
| Q3 | I3 | Q2 | I2 | Q1 | I1 | Q0 | I0 |
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
etc...
What are you thoughts about this?
Eric
First off, current USRP words are 16-bit, are they not? The rx_buffer
module in the FPGA code stores data in a 16-bit FIFO. Are you
suggesting changing this, or is the 32-bit width above merely
illustrative?
illustrative.
Either way, I agree with your sample ordering above.
It's consistent for all sample widths, and it should make host-side code
straight-forward.
OK, good. "Make it so" :-)
Eric
g
And who should I notify (this list?) when this is ready for peer
review? I'm doing my own validation right now, which is going well.
--Paul
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