I would like to change the USRP master clock to 10MHz. I call urx->set_fpga_master_clock_freq(10e6) prior to usrp_standard_rx::make.
I wonder how to set the REFCLK_DIVISOR in db_dbs_rx::_refclk_divisor(). >From all examples I have seen the (master_clock/REFCLK_DIVISOR) is 4MHz. This would mean REFCLK_DIVISOR must be 2.5, but on the other hand it must be an integer.. Can I set the REFCLK_DIVISOR to 3 (resulting in Max2118 clock 3.33MHz)? Or would you recommend something else? -- View this message in context: http://www.nabble.com/USRP1-DBSRX-10MHz-reference-clock-tp24056670p24056670.html Sent from the GnuRadio mailing list archive at Nabble.com. _______________________________________________ Discuss-gnuradio mailing list [email protected] http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
